The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

The present invention provides a thin film transistor, a fabricating method thereof, an array substrate and a display device. The fabricating method of the thin film transistor of the present invention comprises: forming an inducing layer film and an oxide active layer film in contact therewith on a substrate, the oxide active layer film being provided above or below the inducing layer film; and heating the substrate subjected to the above step, crystallizing the oxide active layer film through inducement of the inducing layer film to form a crystalline oxide active layer.

Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 510.sup.15/cm.sup.2 and less than or equal to 510.sup.16/cm.sup.2, or greater than or equal to 510.sup.15/cm.sup.2 and less than or equal to 310.sup.16/cm.sup.2.

The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element.

As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.

The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (53) with ion doping process; the method implements the patterning process to the bottom gate isolation layer (31) and the top gate isolation layer (32) at the same time with one photo process; the method implements patterning process to the second, third metal layers at the same time to obtain the first source (81), the first drain (82), the second source (83), the second drain (84), the first top gate (71) and the second top gate (72) with one photo process; the method implements patterning process to the second flat layer (9), the passivation layer (8) and the top gate isolation layer (32) at the same time with one photo process, to reduce the number of the photo processes to nine for effectively simplifying the manufacture process, raising the production efficiency and lowering the production cost.

A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.

Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 m or longer and 6.5 m or shorter.

An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, in which the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. Hillock generated by the aluminum metal layer in a high temperature environment can be inhibited so as to avoid short-circuiting generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.

A TFT substrate includes a base plate on which first and second gate electrodes respectively corresponding to first and second TFTs are formed. A gate insulation layer, a semiconductor layer, and an etch stop layer are sequentially formed on the base plate and the first and second electrodes. A single photolithographic process is conducted simultaneously on the gate insulation layer, the semiconductor layer, and the etch stop layer with the same gray tone mask to form separate semiconductor portions for the two TFTs and also form contact holes in the etch stop layer and the gate insulation layer to receive sources and drains of the two TFTs to be deposited therein and in contact with the two semiconductor portions.