A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.

A graphene-based valley filter includes a bottom gate, a bilayer graphene and two top gates. The bilayer graphene is deposited on the bottom gate and includes scattering defects. The top gates are deposited on the bilayer graphene. The top gates define a channel in the bilayer graphene, and the scattering defects are located in the vicinity of the channel. A vertical electric field is formed to open a band gap and produce electronic energy subbands in the channel. A transverse in-plane electric field is formed to produce pseudospin splitting in the subbands of the bilayer graphene. The scattering defects are for producing scattering between two opposite energy valley states of the bilayer graphene, couples subband states of opposite pseudospins and opens a pseudogap at a crossing point of the two subbands. Electrons are passed through the channel to become valley polarized in the bilayer graphene.

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

A semiconductor device includes a transistor and a capacitor. The transistor includes a first conductive film; a first insulating film including a film containing hydrogen; a second insulating film including an oxide insulating film; an oxide semiconductor film including a first region and a pair of second regions; a pair of electrodes; a gate insulating film; and a second conductive film. The capacitor includes a lower electrode, an inter-electrode insulating film, and an upper electrode. The lower electrode contains the same material as the first conductive film. The inter-electrode insulating film includes a third insulating film containing the same material as the first insulating film and a fourth insulating film containing the same material as the gate insulating film. The upper electrode contains the same material as the second conductive film. A fifth insulating film containing hydrogen is provided over the transistor.

A change in electrical characteristics can be inhibited and reliability can be improved in a semiconductor device including an oxide semiconductor. The semiconductor device including an oxide semiconductor film includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a third insulating film over the second insulating film. The second insulating film includes oxygen and silicon, the third insulating film includes nitrogen and silicon, and indium is included in a vicinity of an interface between the second insulating film and the third insulating film.

The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a polysilicon layer (3) is formed by implanting a induced ion solid-phase crystallization into an amorphous silicon layer (3), patterning the polysilicon layer using a half-tone mask to form an island active layer (4), and at the same time, etching a upper layer portion (31) with more implanted induced ions located in the middle portion of the island active layer (4) to form a channel region, retaining the upper layer portion (31) with more implanted induced ions located in two sides of the island active layer (4) to form a source/drain contact region, it not only reduces the number of masks, but also saves a process only for implanting doped ion into the source/drain contact region, thereby simplifying the process and reducing production cost.

A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a layer provided below and in contact with the first film is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

A metal element of a metal film is introduced into the oxide semiconductor film by performing heat treatment in the state where the oxide semiconductor film is in contact with the metal film, so that a low-resistance region having resistance lower than that of a channel formation region is formed. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. After that, an unnecessary metal film is removed. Thus, the metal oxide insulating film can be formed over the low-resistance region.

Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.