A process for manufacturing an electroluminescent device, comprising: (a) using a stack comprising, successively: a substrate having a surface; matrix arrays of pixels formed on the surface of the substrate, of columnar shape; an encapsulating layer arranged to cover the matrix arrays of pixels; a dielectric layer formed on the encapsulating layer; (b) performing a directional etch along the normal to the surface of the substrate, of a portion of the dielectric layer extending between the pixels of the matrix arrays of pixels; the dielectric layer having a portion remaining at the end of step (b); and (c) performing a selective chemical etch of the remaining portion of the dielectric layer with a chemical etchant that permits selective etching of the remaining portion of the dielectric layer with respect to the encapsulating layer.

A semiconductor heterostructure for an optoelectronic device with improved light emission is disclosed. The heterostructure can include a first semiconductor layer having a first index of refraction n1. A second semiconductor layer can be located over the first semiconductor layer. The second semiconductor layer can include a laminate of semiconductor sublayers having an effective index of refraction n2. A third semiconductor layer having a third index of refraction n3 can be located over the second semiconductor layer. The first index of refraction n1 is greater than the second index of refraction n2, which is greater than the third index of refraction n3.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A light-emitting diode manufacturing method including the forming of three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, each having a lower portion and a flared upper portion inscribed within a frustum of half apical angle . The method further comprises, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor layer of the III-V compound covering the active area by vapor deposition at a pressure lower than 10 mPa, by using a flux of the group-III element along a direction inclined by an angle III and a flux of the group-V element along a direction inclined by an angle V with respect to the vertical axis, angles III and V being smaller than angle .

A light emitting diode including a substrate having a first area and a second area defined by an isolation groove line, a semiconductor stack disposed on the substrate and including a lower semiconductor layer, an upper semiconductor layer, an active layer, a first electrode pad electrically connected to the lower semiconductor layer, a second electrode pad electrically connected to the upper semiconductor layer, and a connecting portion electrically connecting the semiconductor stack disposed in the first and second areas to each other, and including a first portion, a second portion, and a third portion extending from a second distal end of the first portion, in which the isolation groove line is disposed between the first and second electrode pads and exposes the substrate, the first portion extends along a first direction substantially parallel to an extending direction of the isolation groove line, and the second and third portions extend in a second direction crossing the first direction.

A method for manufacturing a light emitting device can include providing a substrate, forming a first active layer including a first electrical polarity, forming a light emitting region, forming a second active layer including a second electrical polarity, and forming a first electrical contact layer. The light emitting region can emit light with a target wavelength between 200 nm and 300 nm. A plurality of mesas can be formed, where each mesa can include a portion of the first active layer, the light emitting region, the second active layer, and the first electrical contact layer. A mesa width of each mesa is smaller than twice a current spreading length of the light emitting device. In some cases, the current spreading length is from 400 nm to 5 microns. In some cases, a distance separating the mesas from 1 micron to 10 microns.

A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer located over the n-type nitride semiconductor layer and having a V-pit, an active layer located on the V-pit generation layer, and a p-type nitride semiconductor layer located on the active layer. The active layer includes a well layer, which includes a first well layer portion formed along a flat surface of the V-pit generation layer and a second well layer portion formed in the V-pit of the V-pit generation layer. The active layer emits light having at least two peak wavelengths at a single chip level.

An array of semiconductor structures is grown on a hetero-interface barrier layer by forming successive semiconductor layers within holes formed through a dielectric layer deposited above the hetero-interface barrier layer. The hetero-interface forms a two dimensional charge carrier gas. Each semiconductor structure is grown within one of the holes and includes at least one LED active layer between an n-type semiconductor layer and a p-type semiconductor layer. The bottom one of the two semiconductor layers has the same conductivity type as the barrier layer on which it is formed. The hetero-interface is defined between the barrier layer and a buffer layer. The barrier layer and buffer layer can be formed from GaN, AlGaN, and/or InGaN of varying concentrations. The two dimensional charge carrier gas can be a 2D electron gas or a 2D hole gas.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A light-emitting diode 100 includes a first region 1, for example of the P type, formed in a first layer 10 and forming, in a direction normal to a basal plane, a stack with a second region 2 having at least one quantum well formed in a second layer 20, and including a third region 3, for example of the N type, extending in the direction normal to the plane, bordering and in contact with the first and second regions 1, 2, through the first and second layers 10, 20. A process for producing a light-emitting diode 100 in which the third region 3 is formed by implantation into and through the first and second layers 10, 20.