Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

A three-dimensional structure with an FD-SOI transistor includes a handler wafer, a first device layer and a second device layer stacked in sequence from bottom to top. The first device layer includes a first SOI layer, a first FD-SOI transistor and a first back gate. The first SOI layer includes a first front side and a first back side. The first FD-SOI transistor is disposed on the first front side. The first back gate is disposed on the first back side. The second device layer includes a second SOI layer, a second FD-SOI transistor and a second back gate. The second SOI layer includes a second front side and a second back side. The second FD-SOI transistor is disposed on the second front side. The second back gate is disposed on the second back side.

A microelectronic device includes a field-effect n-MOS transistor, a first N-doped zone, constituting one from among the drain and the source of the n-MOS transistor and a second N-doped zone, constituting the other from among the drain and the source of the n-MOS transistor. The device further includes a field-effect p-MOS transistor, a first P-doped zone, constituting one from among the drain and the source of the p-MOS transistor, a dielectric layer in contact with the doped zones and a rear gate. The n-MOS transistor and the p-MOS transistor are separated by a PN junction.

In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.

The present description concerns a transistor comprising a channel region extending in a first direction between a drain region and a source region of a semiconductor layer and a gate structure topping the channel-forming region and comprising a gate insulator topped with a gate region; the channel-forming region comprising a first epitaxial channel region having a first length in the first direction, and a second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and the gate insulator comprising first portions having a first thickness on either side of the first channel region, and a second portion of a second thickness on the first channel region, the second thickness being smaller than the first thickn

Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.

A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

A power device and a manufacturing method thereof are provided. The power device includes a compound semiconductor composite layer, a P-type gate layer, a source, a drain, and a gate electrode layer. The P-type gate layer, the source and the drain are all disposed on the compound semiconductor composite layer. The gate electrode layer is disposed on the P-type gate layer. A sidewall of the P-type gate layer facing towards the drain includes a P-type gate slope, and the P-type gate slope is inclined towards the source relative to a surface of the compound semiconductor composite layer.