A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.

A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

A method comprises forming a buried layer over a substrate, forming an epitaxial layer over the buried layer, forming a first trench and a second trench in the buried layer and the epitaxial layer, wherein a width of the second trench is greater than a width of the first trench, depositing a dielectric layer in the first trench and the second trench, wherein the dielectric layer partially fills the second trench, removing the dielectric layer in the second trench and forming a first gate region in the first trench and a second gate region in the second trench.

A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.

A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.

A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

A nitride semiconductor transistor device is disclosed to provide a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting charge stored in the charge storage layer.

The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (fin), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.