A method of manufacturing a vertical silicon carbide semiconductor device having an electrode on each of two main surfaces of a semiconductor chip in which an n-type low concentration buffer layer and an epitaxial layer are grown by epitaxy on a silicon carbide substrate. Defects extending from the silicon carbide substrate to the epitaxial layer and defects generated in the epitaxial layer during epitaxial growth are detected by a PL image of the n-type low concentration buffer layer; the defects generated in the epitaxial layer during the epitaxy are detected by a PL image of the epitaxial layer; the defects extending from the silicon carbide substrate to the epitaxial layer are detected by the difference between detection results; and semiconductor chips free of the defects extending from the silicon carbide substrate to the epitaxial layer are identified.

A semiconductor device includes a chip that has a first main surface on one side and a second main surface on the other side, an IGBT region provided in an inner portion of the first main surface, an outer peripheral region provided in a peripheral edge portion of the first main surface, a first conductivity type well region formed in a surface layer portion of the first main surface in the outer peripheral region so as to define the IGBT region, an insulating film that covers the well region, a well connection electrode embedded in the insulating film so as to be connected to the well region, and a second conductivity type cathode region formed in a surface layer portion of the second main surface in the outer peripheral region so as to oppose the well connection electrode, and that forms a diode with the well region.

The photodetector is formed in a silicon carbide body formed by a first epitaxial layer of an N type and a second epitaxial layer of a P type. The first and second epitaxial layers are arranged on each other and form a body surface including a projecting portion, a sloped lateral portion, and an edge portion. An insulating edge region extends over the sloped lateral portion and the edge portion. An anode region is formed by the second epitaxial layer and is delimited by the projecting portion and by the sloped lateral portion. The first epitaxial layer forms a cathode region underneath the anode region. A buried region of an N type, with a higher doping level than the first epitaxial layer, extends between the anode and cathode regions, underneath the projecting portion, at a distance from the sloped lateral portion as well as from the edge region.

At a front surface of a silicon carbide base, an n.sup.-type drift layer, a p-type base layer, a first n.sup.+-type source region, a second n.sup.+-type source region, and a trench that penetrates the first and the second n.sup.+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode.

A semiconductor device includes a semiconductor layer having a first surface and a second surface at an opposite side thereto, a bottom gate region of a first conductivity type that is formed in the semiconductor layer, and a top gate region of the first conductivity type that is formed in a surface layer portion of the first surface of the semiconductor layer and faces the bottom gate region in a thickness direction of the semiconductor layer, the bottom gate region includes a first bottom gate region at the source region side and a second bottom gate region at the drain region side, and an interval in the thickness direction between the second bottom gate region and the top gate region is greater than an interval in the thickness direction between the first bottom gate region and the top gate region.

Disclosed is a silicon carbide power semiconductor device and, more particularly, a silicon carbide power semiconductor device capable of improving on-resistance characteristics by contacting at least one lowermost surface of a base or a source with an underlying JFET region.

A SiC semiconductor device having high pressure resistance properties is disclosed. The present invention provides a SiC semiconductor device comprising: a SiC substrate having a first surface and a second surface; an insulating area formed on the second surface side inside the SiC substrate; and a plurality of semiconductor areas including a source area, a base area, and a drain area formed along the first surface on the insulating area, wherein the SiC semiconductor device has a P/N junction parallel to the first surface, the P/N junction extending from the base area toward the drain area on the insulating area and being formed by a first auxiliary region of a first conductive type which is the same conductive type as the source area and a second auxiliary region of a second conductive type which is opposed to the first conductive type.

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

A termination region of an IGBT is described, in which surface p-rings are combined with oxide/polysilicon-filled trenches, buried p-rings and surface field plates, so as to obtain an improved distribution of potential field lines in the termination region. The combination of surface ring termination and deep ring termination offers a significant reduction in the amount silicon area which is required for the termination region.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.