A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

A semiconductor device according to an embodiment includes first to third semiconductor regions, a structure body, a gate electrode, and a high resistance part. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The conductive part is located in the insulating part. The conductive part includes a portion facing the first semiconductor region. The high resistance part is located in the first semiconductor region and has a higher electrical resistance than the first semiconductor region. A plurality of the structure bodies includes first to third structure bodies. The second and third structure bodies are next to the first structure body. The high resistance part overlaps a circle center of an imaginary circle passing through centers of the first to third structure bodies.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

A field effect transistor includes first section and second sections. The first section includes a drift layer. A first P-well is disposed over the drift layer. A first N-source is disposed over the first P-well. A first channel is disposed in an upper portion of the first P-well. The second section includes an area P-well disposed within the drift layer and formed integral with the first P-well. The area P-well includes sidewalls that extend upwards from the drift layer to form an enclosed structure with an outer perimeter and an inner perimeter. An area N-source surrounds the outer perimeter and is formed integral with the first N-source. An upwardly extending intermediate portion of the drift layer extends upwards though the inner perimeter. A second channel is disposed in an upper portion of the sidewalls and is bounded by the inner perimeter and outer perimeter of the sidewalls.

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

A semiconductor device includes a drift layer 20 of a first conductivity type, a base layer 30 of a second conductivity type that is disposed on the drift layer 20 and is connected to a source electrode 90, and a column layer 50 of a second conductivity type that is connected to the source electrode 90 and penetrates the base layer 30 to extend into the drift layer 20.

A semiconductor wafer processing system for processing a semiconductor wafer is presented. The semiconductor wafer processing system comprises: a trench production apparatus configured to produce trenches in the semiconductor wafer, the trenches being arranged next to each other along a first lateral direction (X); a trench filling apparatus configured to epitaxially fill the trenches with a doped semiconductor material; and a controller operatively coupled to at least one of the trench production apparatus and the trench filling apparatus, wherein the controller is configured to control at least one of the trench production apparatus and the trench filling apparatus in dependence of a parameter, the parameter being indicative of at least one of a variation of dopant concentrations of the doped semiconductor material along the first lateral direction (X) that is to be expected when carrying out the epitaxially filling and a deviation of an expected average of the dopant concentrations from a predetermined nominal value.

A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.

A semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.