A method of producing a semiconductor layer sequence includes providing a growth substrate having a growth surface on a growth side, growing a first nitride semiconductor layer on the growth side, growing a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the second nitride semiconductor layer includes at least one opening or at least one opening is produced in the second nitride semiconductor layer or at least one opening is created in the second nitride semiconductor layer during the growing process, removing at least one part of the first nitride semiconductor layer through the openings in the second nitride semiconductor layer, and growing a third nitride semiconductor layer on the second nitride semiconductor layer, wherein the third nitride semiconductor layer covers the openings at least in places.

There are disclosed herein various implementations of a semiconductor component including one or more aluminum silicon nitride layers. The semiconductor component includes a substrate, a group III-V intermediate body situated over the substrate, a group III-V buffer layer situated over the group III-V intermediate body, and a group III-V device fabricated over the group III-V buffer layer. The group III-V intermediate body includes the one or more aluminum silicon nitride layers.

A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. One well layer is disposed between every two barrier layers. The barrier layer is made of Al.sub.xIn.sub.yGa.sub.1-x-yN (0<x<1, 0<y<1, 0<x+y<1) while the well layer is made of In.sub.zGa.sub.1-zN (0<z<1). Thereby quaternary composition is adjusted for lattice match between the barrier layers and the well layers. Thus crystal defect caused by lattice mismatch is improved.

Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.

A structure of a high luminance LED and a high luminance LD is provided. The present invention provides a light emitting device containing, on a zinc blend-type BP layer formed on an Si substrate, an Al.sub.yIn.sub.xGa.sub.zN (y0, x>0) crystal as a mother crystal maintaining the zinc blend-type crystal structure and In dots having an In concentration higher than that of the Al.sub.yIn.sub.xGa.sub.zN (y0, x>0) crystal as the mother crystal.

A semiconductor light emitting device including an N-type semiconductor layer, a P-type semiconductor layer, a light emitting layer and a strain relief layer is provided. The light emitting layer is disposed between the N-type semiconductor layer and the P-type semiconductor layer, and the light emitting layer is a multiple quantum well structure. The strain relief layer is disposed between the light emitting layer and the N-type semiconductor layer, and is made of In.sub.xGa.sub.1-xN, where 0<x<1. The difference between any two values of x corresponded to any two positions in the strain relief layer is greater than 0.01 and less than 0.01. The thickness of the strain relief layer is larger than the thickness of each well layer of the multiple quantum well structure.

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

Described herein is a method for manufacturing a stack of semiconductor materials in which a growth substrate is separated from the stack after a semiconductor material, e.g., a Group III nitride semiconductor material, is grown on the substrate. The separation is effected in a spalling procedure in which spalling-facilitating layers are deposited over a protective cap layer that is formed over the Group III-nitride semiconductor material. Such spalling-facilitating layers may include a handle layer, a stressor layer, and an optional adhesion layer. The protective cap layer protects the Group III-nitride from being damaged by the depositing of one or more of the spalling-facilitating layers. After spalling to remove the growth substrate, additional processing steps are taken to provide a semiconductor device that includes undamaged semiconductor material. In one arrangement, the semiconductor material is GaN and includes p-doped GaN region that was undamaged during manufacturing.