Disclosed is a semiconductor light emitting device including: a plurality of semiconductor layers; a non-conductive reflective film which is formed on the plurality of semiconductor layers; and first and second electrodes formed on the non-conductive reflective film, wherein a spacing between the first electrode and the second electrode is 80 m or greater, and a ratio of a combined area of the first and second electrodes to a planform area of the semiconductor light emitting device as seen on a top view is 0.7:1 or less.

A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor structure. A filler material can penetrate at least some of the plurality of pores and directly contact the surface of the semiconductor structure. In an illustrative embodiment, multiple types of filler material at least partially fill the pores of the aluminum oxide layer.

A nitride semiconductor light-emitting element includes a substrate; and an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. The n-type nitride semiconductor layer includes a first n-type nitride semiconductor layer, a second n-type nitride semiconductor layer, and a third n-type nitride semiconductor layer. The n-type dopant concentration in the second n-type nitride semiconductor layer is lower than that in the first n-type nitride semiconductor layer. The n-type dopant concentration in the third n-type nitride semiconductor layer is higher than that in the second n-type nitride semiconductor layer. A V-pit structure is partially formed in the second n-type nitride semiconductor layer, the third n-type nitride semiconductor layers, and the light-emitting layer. The average position of the starting point of the V-pit structure is present in the second n-type nitride semiconductor layer.

Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (Al.sub.xGa.sub.1-xN) sub-layers. Each of the sub-layers has a respective value for x that is between 0 and 1. A value of x for each sub-layer is a function of its position within the second buffer layer. A first gallium nitride (GaN) layer is epitaxially grown over the second buffer layer. A third buffer layer is then epitaxially grown over the first GaN layer. A second GaN layer is then epitaxially grown over the third buffer layer.

A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

A nitride semiconductor structure including a substrate, a cap layer, a nucleation layer, a transition layer and a composite buffer structure is provided. The cap layer is located on the substrate. The nucleation layer is located between the substrate and the cap layer. The transition layer is located between the nucleation layer and the cap layer, wherein the transition layer is an Al.sub.xGaN layer. The composite buffer structure is located between the transition layer and the cap layer. The composite buffer structure includes a first composite buffer layer, wherein the first composite buffer layer includes a plurality of first Al.sub.yGaN layers and a plurality of first GaN layers alternately stacking with each other, and the x is equal to the y.

In various embodiments, light-emitting devices incorporate smooth contact layers and polarization doping (i.e., underlying layers substantially free of dopant impurities) and exhibit high photon extraction efficiencies.

A manufacturing method of a light-emitting device comprising a first light semiconductor stack and a second semiconductor stack on thereof comprises steps of: providing a substrate with a top surface; forming a semiconductor stack on the substrate; forming a trench in the semiconductor stack to define multiple second semiconductor stacks and expose a first upper surface; forming a scribing region in the first upper surface to define multiple first semiconductor stacks; etching the scribing region to form a first side wall of each of the first semiconductor stack; and dividing the substrate along the scribing region to form multiple light-emitting devices, wherein the first side wall and the top surface form an acute angle between thereof, and 3080, and a side surface of the substrate directly connects the top surface after the dividing step.

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.