A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in the surface portion of the semiconductor layer with each body region forming a unit cell, a source region of the first conductivity type formed in the inner portion of the body region, a gate electrode facing the body region across a gate insulating film, a drain region of the first conductivity type and a collector region of the second conductivity type formed in the rear surface portion of the semiconductor layer such that the drain region and the collector region adjoin each other, and a drift region between the body region and the drain region, wherein the collector region is formed such that the collector region covers a region including at least two unit cells in the x-axis direction along the surface of the semiconductor layer.

An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.

The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

A method of manufacturing a structure in a semiconductor body comprises forming a first mask above a first surface of the semiconductor body. The first mask comprises an opening surrounding a first portion of the first mask, thereby separating the first portion and a second portion of the first mask. The semiconductor body is processed through the opening at the first surface. The opening is increased by removing at least part of the first mask in the first portion while maintaining the first mask in the second portion. The semiconductor body is further processed through the opening at the first surface.

A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate, a source disposed in the N-well and a drain disposed in the P-well, a shallow trench isolation (STI) structure disposed in the P-well, a gate structure disposed on the semiconductor substrate, wherein a portion of the gate structure extends into the semiconductor substrate and is disposed in a location corresponding to the STI structure.

In accordance with an embodiment, a cascode connected semiconductor component and a method for manufacturing the cascode connected semiconductor component are provided. The cascode connected semiconductor component has a pair of silicon based transistors, each having a body region, a gate region over the body region, a source region and a drain. The source regions of a first and second silicon based transistor are electrically connected together and the drain regions of the first and second silicon based transistors are electrically connected together. The gate region of the second silicon based transistor is connected to the drain regions of the first and second silicon based transistors. The body region of the second silicon based transistor has a dopant concentration that is greater than the dopant concentration of the first silicon based transistor. A gallium nitride based transistor has a source region coupled to the first and second silicon based transistor.

A 3D trenched MOSFET device includes a semiconductor substrate, an epitaxial layer, an epitaxial layer, a doped area, first doped wells, second doped wells, a trenched gate, first heavily-doped areas, a patterned insulation layer, and a conduction layer. The epitaxial layer is formed on the semiconductor substrate. The doped area, the first doped wells, and the second doped wells are formed in the epitaxial layer. The trenched gate, formed in the epitaxial layer and the first doped wells, penetrates through the doped area and surrounds the second doped wells. The bottoms of the first doped wells and the second doped wells are lower than the bottom of the trenched gate. The first heavily-doped areas are formed in the doped area. The first heavily-doped areas respectively surround the second doped wells and the trenched gate surrounds the first heavily-doped areas.

A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.