A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal.

A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the second current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the first current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is configured as a two terminal device.

In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.

A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.

An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.