A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases.

A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 110.sup.14 atoms/atomscm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.

A method for producing an epitaxial silicon wafer by applying a vapor deposition on a silicon wafer is disclosed. A vapor deposition apparatus in which the vapor deposition is conducted at least includes a chamber and a hydrogen-chloride-gas supply apparatus that is in communication and connected with an inside of the chamber to supply hydrogen chloride gas into the chamber. A valve including a diaphragm that allows or blocks a flow of the hydrogen chloride gas from an inlet channel to an outlet channel is disposed in the hydrogen-chloride-gas supply apparatus. A W-free anticorrosion alloy material is used for the diaphragm. When a maintenance work is to be done inside the chamber, the hydrogen chloride gas is supplied from the hydrogen-chloride-gas supply apparatus into the chamber.

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

A silicon carbide semiconductor device includes an impurity region including a p type impurity and disposed within a silicon carbide layer to surround an element region as seen in plan view. The impurity region has a peak concentration of the p type impurity at a position within the silicon carbide layer distant from a first main surface. The peak concentration is not less than 110.sup.16 cm.sup.3 and not more than 510.sup.17 cm.sup.3. The impurity region is formed by implanting ions of the p type impurity into the silicon carbide layer. Then, a silicon dioxide film is formed to cover the first main surface of the silicon carbide layer by performing a thermal oxidation process on the silicon carbide layer, and the concentration of the p type impurity in the vicinity of the first main surface is lowered.

Provided is an SOI substrate which has a substrate, an insulating layer formed over the substrate, and a semiconductor layer formed over the insulating layer. Optical waveguides are formed in the semiconductor layer of the SOI substrate. This substrate has a low resistance semiconductor layer and a high resistance semiconductor layer thereover. Further, wirings which are formed through insulating films are provided on the optical waveguides. In this manner, the low resistance semiconductor layer is arranged in the surface part of the substrate of the insulating films, thereby restraining an eddy current generated in the substrate due to an electric signal transmitted through the wirings.

Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.