A doping method for an array substrate and a manufacturing equipment. The doping method comprises: using a halftone mask to form a photoresist pattern layer on a gate insulation layer of a substrate; wherein, a polysilicon pattern layer is disposed on the substrate; the gate insulation layer covers the polysilicon pattern layer; the photoresist pattern layer corresponding to a heavily doping region forms a hollow portion; the photoresist pattern layer corresponding to a lightly doping region forms a first photoresist portion; the photoresist pattern layer corresponding to an undoped region forms a second photoresist portion; the first photoresist portion is thinner than the second photoresist portion; and performing one doping process to the polysilicon pattern layer such that the heavily doping region and the lightly doping region of the polysilicon pattern layer are formed simultaneously in order to reduce the manufacturing process of an LTPS array substrate.

Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as a, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as b, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Provided are a thin film transistor (TFT) substrate, a display device, and a method of forming the TFT. A TFT substrate includes: a first TFT including: a polycrystalline semiconductor (PS) layer, a first gate electrode (GE) overlapping the PS layer, a nitride layer (NL) on the first GE, an oxide layer (OL) on the NL, and a first source electrode and a first drain electrode on the OL, and a second TFT including: a second GE on a same layer as the first GE, a hydrogen collecting layer between the second GE and the NL, an oxide semiconductor (OS) layer on the OL, a second source electrode and a second drain electrode contacting respective sides of the OS layer, wherein the first TFT and the second TFT are disposed on a same substrate, and wherein the NL includes an opening exposing the hydrogen collecting layer of the second TFT.

Embodiments of the invention provides a method for fabricating an array substrate comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type.

An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate patterning the metal film by one patterning process, and forming patterns of a gate electrode a source electrode, a drain electrode a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion, a pixel electrode and a bridge structure.

A method of manufacturing a display panel having a plurality of lightly doped drain thin film transistors arranged as a matrix includes forming a semiconductor pattern with a predetermined shape on a substrate; forming a dielectric layer covering the semiconductor pattern on the substrate; forming a metal layer on the dielectric layer; forming a photoresist patterns smaller than the semiconductor pattern on the metal layer above the semiconductor pattern; etching the metal layer to form a gate electrode smaller than the photoresist pattern; doping high concentration ions by using the photoresist pattern as a mask to form a pair of highly doped regions on the semiconductor pattern not covered by the photoresist pattern; removing the photoresist pattern; and doping low concentration ions by using the gate electrode as a mask to form a pair of lightly doped regions between the highly doped regions and a part of the semiconductor pattern.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

A display device includes: a first wiring line and a second wiring line separated from each other on a substrate; a gate insulating layer on the first wiring line and the second wiring line; a step difference compensation pattern between the first wiring line and the second wiring line on the gate insulating layer; a protective layer on the step difference compensation pattern; and a pixel electrode on the protective layer.

A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region.