A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.

A preparation method of a poly-silicon thin film transistor (TFT) array substrate and an array substrate thereof are provided. The preparation method includes: forming a photoresist layer on a poly-silicon layer, and exposing and developing the photoresist layer with a gray tone mask to form patterns of a photoresist completely-reserved region, a photoresist partially-reserved regions and a photoresist completely-removed region; removing part of the poly-silicon layer located in the photoresist completely-removed region, to form patterns of active layers; ashing the photoresist so as to expose part of the active layer located in the photoresist partially-reserved regions and inject P+ions of high concentration into the part of the active layer, to form doping regions of patterns of source-drain electrodes of a P-type TFT; and stripping off remaining photoresist.

A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.

Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present invention, there is provided a liquid crystal display device, including a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein a diffusion prevention pattern is disposed on the semiconductor pattern layer to prevent diffusion into the semiconductor pattern layer or to maintain uniform thickness of the semiconductor pattern layer.

One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

A method of forming a patterned metal film layer and preparation methods of a transistor and an array substrate are disclosed, in the technical field of displays. The method of forming a patterned metal film layer of the invention comprises: sequentially depositing a sacrificial layer and a photoresist layer on a substrate, and forming a patterned sacrificial layer and a patterned photoresist layer overlying on the patterned sacrificial layer by exposure, development, and etching, wherein a side wall of the patterned sacrificial layer adjacent to a patterned metal film layer to be formed forms a chamfer; depositing a metal film layer on the substrate after finishing the above step, and removing the patterned photoresist layer and the sacrificial layer to form a patterned metal film layer.

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n.sup.-type impurity regions are formed between a channel formation region and n.sup.+-type impurity regions. Some of the n.sup.-type impurity regions overlap with a gate electrode, and the other n.sup.-type impurity regions do not overlap with the gate electrode. Since the two kinds of n.sup.-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

A display substrate includes a pixel switching element, a pixel electrode, a reference line, a control switching element, a bias line, a light sensing element, a sensing capacitor and a light blocking filter pattern. The pixel switching element is connected to a data line and a gate line, includes a first semiconductor pattern. The pixel electrode is connected to the pixel switching element. The reference line is in parallel with the data line. The control switching element is connected to the reference line and the gate line, includes a second semiconductor pattern. The bias line is in parallel with the gate line. The light sensing element is connected to the bias line and the control switching element, includes a third semiconductor pattern. The sensing capacitor is connected to the light sensing element and a storage line. The light blocking filter pattern transmits a first light, and blocks a second light.

The present disclosure provides a TFT, a method for manufacturing the same, an array substrate and a display device, so as to effectively reduce a TFT edge leakage current I.sub.OFF (edge). The TFT includes an active layer and a silicon oxide layer arranged at a lateral side of the active layer.

A method of manufacturing a display apparatus includes: preparing a substrate including a pixel circuit region and a driving circuit region; forming a first active layer at the pixel circuit region; forming a second active layer at the driving circuit region; forming gate electrodes that overlap the first active layer and the second active layer, respectively, with a gate insulating layer disposed therebetween; forming a first insulating layer covering the first and second active layers; forming a first contact hole that passes through the first insulating layer until a portion of the first active layer is exposed; heat-treating the substrate where the first insulating layer, in which the first contact hole is formed, is formed; and forming a second contact hole that passes through the first insulating layer disposed on the heat-treated substrate until a portion of the second active layer is exposed.