LTPS TFT Substrate Structure and Method of Forming the Same

Abstract

A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.

Claims

1. A method of forming a low temperature poly-Si (LTPS) thin-film transistor (TFT) substrate, comprising: Step 1: providing a substrate and depositing a buffer layer on the substrate; Step 2: depositing an a-Si layer on the buffer layer; Step 3: depositing a silicon oxide layer on the a-Si layer, and patterning the silicon oxide layer through lithography and etching process, so as to form a silicon oxide layer in the display area; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer, and removing the silicon oxide layer; Step 5: patterning the poly-Si layer through lithography and etching process so to form a first poly-Si region in the display area, and a second poly-Si region in the drive area, with the two regions arrayed with a space in between; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions respectively, and implanting different dosages of P31 into the heavily N-doped area and the lightly N-doped area, so as to form a lightly doped drain (LDD) area; Step 7: depositing and patterning a gate insulating layer on the buffer layer, the first and the second poly-Si regions; Step 8: depositing a first metal layer on the gate insulating layer, and patterning the metal layer to form a first gate and a second gate corresponding to the first and the second poly-Si regions respectively; Step 9: forming an interlayer dielectric layer on the gate insulating layer, and forming via holes leading to the heavily N-doped areas next to the first and second poly-Si regions through the gate insulating layer and the interlayer dielectric layer; and Step 10: depositing and patterning a second metal layer on the interlayer dielectric layer, and forming a first source/drain and a second source/drain; with the first source/drain and the second source/drain connecting to the heavily N-doped areas next to the first and second poly-Si regions through the via hole.

2. The method of claim 1, wherein a material of the buffer layer is one of silicon nitride and silicon oxide, or a combination thereof.

3. The method of claim 1, wherein a material of the interlayer dielectric layer is one of silicon oxide and silicon nitride, or a combination thereof.

4. The method of claim 1, wherein each of the first gate and the second gate is a single layer or stacked layers, and each layer is made of a material selected from molybdenum, titanium, aluminum, and copper.

5. The method of claim 1, wherein in Step 6, the heavily N-doped area and the lightly N-doped area are defined by applying lithographic photoresist and two photomasks respectively, and lightly doped drain areas are produced by implanting different dosages of P31 in the heavily N-doped area and lightly N-doped area.

6. The method of claim 1, wherein the gate insulating layer, the first gate, the second gate, the via holes, the first source/drain and the second source/drain are formed through deposition, lithography and etching process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification.

[0050] FIG. 1 shows a structure diagram of a conventional LTPS TFT substrate.

[0051] FIG. 2 shows a flowchart of a method for forming a LTPS TFT substrate according to a preferred embodiment of the present invention.

[0052] FIG. 3 shows a diagram of step 1 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0053] FIG. 4 shows a diagram of step 2 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0054] FIG. 5 shows a diagram of step 3 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0055] FIGS. 6-7 show a diagram of step 4 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0056] FIG. 8 shows a diagram of step 5 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0057] FIG. 9 shows a diagram of step 6 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0058] FIG. 10 shows a diagram of step 7 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0059] FIG. 11 shows a diagram of step 8 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0060] FIG. 12 shows a diagram of step 9 of the method for forming the LTPS TFT substrate as depicted in FIG. 2.

[0061] FIG. 13 shows a diagram of step 10 of the method for forming the LTPS TFT substrate as depicted in FIG. 2, and a cross-sectional view of the LTPS TFT substrate according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0062] The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0063] Please refer to FIG. 2. The present invention provides a method of forming a LTPS TFT substrate comprising the following steps:

[0064] Step 1: provide a substrate 1, and deposit a buffer layer 2 on the substrate 1, as shown in FIG. 3.

[0065] The substrate 1 is a transparent substrate which is made, preferably, of glass or plastic.

[0066] Specifically, the materials of the buffer layer 2 can be either silicon nitride (SiNx), silicon oxide (SiOx), or the combination of the two.

[0067] Step 2: deposit an a-Si layer 3 on the buffer layer 2, as shown in FIG. 4.

[0068] Step 3: as shown in FIG. 5, deposit a silicon oxide layer on the a-Si layer 3, and pattern the silicon oxide layer through lithography and an etching process so as to get a silicon oxide layer 4 in a display area 11. The a-Si layer 3 in a drive area 12 of the non-display area, at this stage, is not covered by the silicon oxide layer 4, as shown in FIG. 6.

[0069] Step 4: as shown in FIGS. 6 and 7, the silicon oxide layer 4 is taken as a photomask when the a-Si layer 3 is annealed by excimer laser. The a-Si layer 3 thus crystalizes and turns into a poly-Si layer, and the silicon oxide layer 4 is removed.

[0070] When the a-Si layer 3 is annealed by excimer laser, the part in the display area 11 is exposed to relatively lower laser energy as it is covered by the silicon oxide layer 4, so that grains formed in this part are smaller but with better uniformity. The a-Si layer 3 in the drive area 12 is not covered by the silicon oxide layer 4, and therefore it is exposed to higher laser energy and forms relatively larger grains.

[0071] Step 5: as shown in FIG. 8, a first poly-Si region 31 in the display area 11 and a second poly-Si region 32 in the drive area 12 are formed by patterning the poly-Si layer through lithography and etching process. The first poly-Si region 31 and the second poly-Si region 32 are arrayed with a space in between.

[0072] The first poly-Si region 31 in the display area 11 has smaller grains with better uniformity, whereas the second poly-Si region 32 in the drive area 12 has larger grains.

[0073] Step 6: as shown in FIG. 9, a heavily N-doped area and lightly N-doped area are defined respectively on the first poly-Si region 31 and the second poly-Si region 32. Different dosages of P31 (Phosphorus-31) are implanted in the heavily N-doped area and lightly N-doped area respectively to form LDD areas.

[0074] Specifically, the heavily N-doped area and the lightly N-doped area are defined by applying lithographic photoresist and two photomasks, respectively. Different dosages of P31 (Phosphorus-31) are implemented in the heavily N-doped area and lightly N-doped area, so as to form LDD areas.

[0075] Step 7: as shown in FIG. 10, deposit and pattern a gate insulating layer 5 on the buffer layer 2, the first poly-Si region 31 and the second poly-Si region 32.

[0076] Step 8: as shown in FIG. 11, deposit and pattern a first metal layer and form a first gate 61 and a second gate 62 on the gate insulating layer 5 corresponding to the first poly-Si region 31 and the second poly-Si region 32.

[0077] Specifically, each of the first gate 61 and the second gate 62 is a single layer or stacked layers, and each layer is made of a material selected from molybdenum (Mo), titanium (Ti), aluminum (Al) or copper (Cu).

[0078] Step 9: as shown in FIG. 12, form an interlayer dielectric layer 7 on the gate insulating layer 5 and form via holes 70 leading to the heavily N-doped areas next to the first poly-Si region 31 and the second poly-Si region 32 through the gate insulating layer 5 and the interlayer dielectric layer 7.

[0079] Specifically, materials of the interlayer dielectric layer 7 can be silicon nitride (SiNx), silicon oxide (SiOx), or a combi

[0080] Step 10: as shown in FIG. 13, deposit and pattern a second metal layer on the interlayer dielectric layer 7, so as to form a first source/drain 81 and a second source/drain 82.

[0081] The first source/drain 81 and the second source/drain 82 contact the heavily N-doped areas next to the first poly-Si region 31 and the second poly-Si region 32 respectively through the via holes 70. The existing techniques can be applied afterwards so to complete the following procedure, and eventually produce a LTPS TFT substrate.

[0082] Specifically, the gate insulating layer 5, the first gate 61, the second gate 62, the via holes 70, and the first source/drain 81 and the second source/drain 82 are formed through deposition, lithography and etching process.

[0083] The method of forming the LTPS TFT substrate deposits and patterns a layer of silicon oxide on the a-Si layer first, and then anneals the a-Si layer with excimer laser, so as to get a silicon oxide layer on the a-Si layer in the display area 11. Then, the silicon oxide layer serves as a photomask when the a-Si layer is annealed by excimer laser and crystalizes, and turns into a poly-Si layer. It forms larger grains in the drive area 12 and has better electron mobility. The display area 11 is exposed to lower laser energy as it is shielded by the silicon oxide layer, and thus it forms relatively smaller grains with better uniformity. Therefore, the electron mobility in the display area 11 has better uniformity and thus elevates the quality of the LTPS TFT substrate.

[0084] Please refer to FIG. 13. The present invention further provides a LTPS TFT substrate structure, comprising a substrate 1; a buffer layer 2 on the substrate 1; a first poly-Si region 31 and a second poly-Si region 32 arrayed with a space in between on the buffer layer 2; a first source/drain 81 and a second source/drain 82 disposed above the first poly-Si region 31 and second poly-Si region 32; a gate insulating layer 5 installed on the buffer layer 2, the first poly-Si region 31 and second poly-Si region 32; a first gate 61 and a second gate 62 installed on the gate insulating layer 5 corresponding to the first poly-Si region 31 and second poly-Si region 32; and an interlayer dielectric layer 7 installed on the gate insulating layer 5, the first gate 61 and the second gate 62. Both sides of the first poly-Si region 31 and second poly-Si region 32 are next to a heavily N-doped area, which are connected to the first source/drain 81 and the second source/drain 82 through via holes 70.

[0085] The LTPS TFT substrate comprises a display area 11 and a drive area 12. The first poly-Si region 31 is in the display area 11 of the LTPS TFT substrate, and the second poly-Si region 32 is in the drive area 12 of the LTPS TFT substrate. The grains of the first poly-Si region 31 are smaller than those of the second poly-Si region 32, yet the uniformity of the grains of the first poly-Si region 31 is larger than that of the second poly-Si region 32.

[0086] A substrate 1 is a transparent substrate which is made, preferably, of glass or plastic.

[0087] Specifically, materials of the buffer layer 2 and the interlayer dieletric layer 7 can be either silicon nitride (SiNx), silicon oxide (SiOx), or the combination of the two.

[0088] Each of the first gate 61 and the second gate 62 is a single layer or stacked layers, and each layer is made of a material selected from molybdenum (Mo), titanium (Ti), aluminum (Al) or copper (Cu).

[0089] The grains of the poly-Si region of the present LTPS TFT structure are larger in the drive area 12 than in the display area 11, but have better uniformity in the display area 11 than in the drive area 12. Therefore, the drive circuit has better electrical characteristics, and the TFT within the display area 11 has more even electrical property, so that the TFT substrate has better quality.

[0090] In sum, the forming method of the LTPS TFT substrate of the present invention proposes depositing and patterning a layer of silicon oxide on the a-Si layer, and producing a layer of silicon oxide on the a-Si layer in the display area. Then, the silicon oxide layer serves as a photomask when the a-Si layer is annealed by excimer laser and crystalizes, and turns into a poly-Si layer. It forms relatively larger grains in the drive area and attains to higher electron mobility. The display area, because of the shielding of the silicon oxide layer, is exposed to lower laser energy, thus forms relatively smaller grains with better uniformity. It ensures more even electron mobility in the display area and enhances the quality of the LTPS TFT substrate. The forming process is simple and easy to operate. In addition, the present invention provides a LTPS TFT substrate structure with poly-Si regions in the drive area producing larger grains than in the display area, so as to ensure that the drive has better electrical characteristics and the TFT within the display area has more even electrical property. The TFT substrate, therefore, has better quality.

[0091] While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements made without departing from the scope of the broadest interpretation of the appended claims.