The invention provides a method for manufacturing a TFT substrate and a TFT substrate manufactured thereof. In the above TFT substrate, the low temperature poly-silicon layer is produced by solid phase crystallization, the cost of production is under budget, and the TFT substrate is a double-grid structure that can guarantee the electrical characteristics of the thin film transistor and better the capacity of drive, and leakage phenomenon caused by groove light seldom happens.

A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.

Provided is a semiconductor device including a first transistor having an oxide semiconductor film, an interlayer film over the first transistor, and second transistor located over the interlayer film and having a semiconductor film including silicon. The interlayer film can include an inorganic insulator. The semiconductor film including silicon can contain polycrystalline silicon. The interlayer film can include an inorganic insulator.

There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer (11) and a second material layer (12) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer (12) or an interface thereof.

The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

There are provided a method of manufacturing a thin film transistor and a display including a thin film transistor. The method of manufacturing a thin film transistor includes forming a barrier layer cm a substrate, forming a semiconductor layer on the barrier layer, forming a gate insulating layer on the semiconductor layer, forming a gate electrode on the gate insulating layer, forming an offset region on an external surface of the gate electrode through a plasma heat treatment process or an annealing process, etching, an offset region of the gate electrode, etching a gate insulating layer except for a portion of the gate insulating layer, positioned below the gate electrode, forming an interlayer insulating layer on the gate electrode, and etching, the interlayer insulating layer to form a source electrode and a drain electrode.

The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area.

As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.

An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, in which the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. Hillock generated by the aluminum metal layer in a high temperature environment can be inhibited so as to avoid short-circuiting generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.