The present invention relates to a display device including a static electricity discharge circuit. The display device according to an exemplary embodiment of the present invention includes: a thin film transistor array panel including a display area including a plurality of pixels and a peripheral area around the display area; a signal wire positioned at the peripheral area; and a static electricity discharge circuit unit positioned at the peripheral area and connected to the signal wire, wherein the static electricity discharge circuit unit includes a first portion and a second portion positioned at a same layer as a portion of the signal wire and facing each other with a separation space therebetween, and a connecting member positioned at a different layer from the first portion and the second portion and electrically connecting the first portion and the second portion.

A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

The present invention relates to an image sensing device comprising: an image sensing array and an image processing circuit. The image sensing array includes sensing units, and the sensing units respectively generate multiple pieces of pixel data. The multiple pieces of pixel data are generated according to different frame rates under different exposure periods, and include a first pixel data of a first subframe and a second pixel data of a second subframe. The first pixel data is generated by exposing a first exposure period for a first frame rate, and the second pixel data is generated by exposing a second exposure period for a second frame rate. The first frame rate is less than the second frame rate. The first exposure period is greater than the second exposure period, and multiple pieces of the second pixel data are generated during one image capturing operation.

Disclosed is a gate control circuit that generates a gate control signal of an output transistor connected between an application end of a power supply voltage and an application end of an output voltage. The gate control circuit includes a first current source connected between the application end of the power supply voltage and the application end of the output voltage, a second current source connected between an application end of a booster voltage and an application end of a reference voltage, the booster voltage being raised to a voltage value higher than the power supply voltage in a steady state, an output stage that uses at least one of the first and second current sources to generate a gate charge current for charging a gate of the output transistor, and a controller that uses at least one of the first and second current sources according to the output voltage.

The present invention is provided with a Si substrate, an ESD protection circuit formed in the Si substrate, pads formed on the surface of the Si substrate and electrically connected to first and second input/output terminals of the ESD protection circuit, a rewiring layer formed on the surface of the Si substrate for electrically connecting the pads and metal plated films, and an insulating resin film formed on the rear surface of the Si substrate. Thus, provided is an ESD protection device which can suppress the influence of external noise, etc.

Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge protection circuit coupled between the first input node and the first resistor, and a second electrostatic discharge protection circuit coupled between the second input node and the second resistor.