TFT substrate structure

Abstract

The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Claims

1. A thin-film transistor (TFT) substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different; wherein the TFT substrate comprises a substrate, a first active layer formed on the substrate, a first metal layer formed on the substrate and the first active layer, a first insulation layer formed on the first active layer and the first metal layer, and covering the substrate, a second active layer formed on the first insulation layer, a second metal layer formed on the first insulation layer, a third metal layer formed on the second active layer and the first insulation layer, a passivation layer formed on the second active layer and the third metal layer, and covering the first insulation layer, and a pixel electrode layer formed on the passivation layer, and contacting the third metal layer; wherein the first insulation layer is located between the first metal layer and the second metal layer and is also located between the first metal layer and the third metal layer such that the first insulation layer is a gate insulation layer that isolates the first active layer from the second metal layer and also isolates the first metal layer from the second active layer; and wherein the first metal is in contact engagement with the first active and is separated from the second active layer by the first insulation layer; the second metal layer is separated from the first active layer and the first metal layer by the first insulation layer, and is also separated from the second active layer; and the third metal layer is in contact engagement with the second active layer, wherein the Switching TFT that comprises the first active layer also comprises the second metal layer and a part of the first metal layer and the Driving TFT that comprises the second active layer also comprises the third metal layer and a part of the first metal layer.

2. The TFT substrate structure according to claim 1, wherein material of the first active layer and material of the second active layer respectively are amorphous silicon and metal oxide semiconductor, Low Temperature Poly-silicon and amorphous silicon, Low Temperature Poly-silicon and metal oxide semiconductor, or both metal oxide semiconductor.

3. A thin-film transistor (TFT) substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different; wherein the TFT substrate comprises a substrate, a first active layer formed on the substrate, a first metal layer formed on the substrate and the first active layer, a first insulation layer formed on the first active layer and the first metal layer, and covering the substrate, a second active layer formed on the first insulation layer, a second metal layer formed on the first insulation layer, a third metal layer formed on the second active layer and the first insulation layer, a passivation layer formed on the second active layer and the third metal layer, and covering the first insulation layer, and a pixel electrode layer formed on the passivation layer, and contacting the third metal layer; wherein the first insulation layer is located between the first metal layer and the second metal layer and is also located between the first metal layer and the third metal layer such that the first insulation layer is a gate insulation layer that isolates the first active layer from the second metal layer and also isolates the first metal layer from the second active layer; wherein the first metal is in contact engagement with the first active and is separated from the second active layer by the first insulation layer; the second metal layer is separated from the first active layer and the first metal layer by the first insulation layer, and is also separated from the second active layer; and the third metal layer is in contact engagement with the second active layer, wherein the Switching TFT that comprises the first active layer also comprises the second metal layer and a part of the first metal layer and the Driving TFT that comprises the second active layer also comprises the third metal layer and a part of the first metal layer; and wherein material of the first active layer and material of the second active layer respectively are amorphous silicon and metal oxide semiconductor, Low Temperature Poly-silicon and amorphous silicon, Low Temperature Poly-silicon and metal oxide semiconductor, or both metal oxide semiconductor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The technical solution and the beneficial effects of the present invention are best understood from the following detailed description with reference to the accompanying figures and embodiments.

(2) In drawings,

(3) FIG. 1 is a structural diagram of a TFT substrate according to prior art;

(4) FIG. 2 is a structural diagram of a TFT substrate structure according to the first embodiment of the present invention;

(5) FIG. 3 is a structural diagram of a TFT substrate structure according to the second embodiment of the present invention;

(6) FIG. 4 is a structural diagram of a TFT substrate structure according to the third embodiment of the present invention;

(7) FIG. 5 is a structural diagram of a TFT substrate structure according to the fourth embodiment of the present invention;

(8) FIG. 6 is a structural diagram of a TFT substrate structure according to the fifth embodiment of the present invention;

(9) FIG. 7 shows electric property curve diagrams of the metal oxide semiconductor TFTs of the TFT substrate structure according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(10) For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments.

(11) The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different.

(12) Please refer to FIG. 2. The TFT substrate structure according to the first embodiment of the present invention is a combination formation of a top gate structure and a back channel etching (BCE) structure. Specifically, the TFT substrate structure comprises a substrate 1, a first active layer 21 formed on the substrate 1, a first metal layer 31 formed on the substrate 1 and the first active layer 21, a first insulation layer 41 formed on the first active layer 21 and the first metal layer 31, and covering the substrate 1, a second active layer 22 formed on the first insulation layer 41, a second metal layer 32 formed on the first insulation layer 41, a third metal layer 33 formed on the second active layer 22 and the first insulation layer 41, a passivation layer 6 formed on the second active layer 22 and the third metal layer 33, and covering the first insulation layer 41, and a pixel electrode layer 7 formed on the passivation layer 6, and contacting the third metal layer 33.

(13) Specifically, in this structure, the left side of the first metal layer 31 is a source/a drain of a TFT 11, the right side is a gate of a TFT 12, i.e. the gate of the TFT 12 and the drain of the TFT 11 are connected. The second metal layer 32 is a gate of the TFT 11, and the third metal layer 33 is a source/a drain of the TFT 12.

(14) Please refer to FIG. 3. The TFT substrate structure according to the second embodiment of the present invention is a combination formation of two back channel etching (BCE) structures. Specifically, the TFT substrate structure comprises a substrate 1, a first metal layer 31 formed on the substrate 1, a first insulation layer 41 formed on the first metal layer 31, and covering the substrate 1 and the first metal layer 31, a first active layer 21 formed on the first insulation layer 41, a second metal layer 32 formed on the first active layer 31 and the first insulation layer 41, a second insulation layer 42 formed on the second metal layer 32 and the first active layer 21, and covering the first insulation layer 41, a second active layer 22 formed on the second insulation layer 42, a third metal layer 33 formed on the second active layer 22 and the second insulation layer 42, a passivation layer 6 formed on the second active layer 22 and the third metal layer 33, and covering the second insulation layer 42, and a pixel electrode layer 7 formed on the passivation layer 6 and contacting the third metal layer 33.

(15) Specifically, in this structure, the first metal layer 31 is a gate of a TFT 11, the left side of the second metal layer 32 is a source/a drain of a TFT 11, and the right side is a gate of the TFT 12, i.e. the gate of the TFT 12 and the drain of the TFT 11 are connected. The third metal layer 33 is a source/a drain of the TFT 12.

(16) Please refer to FIG. 4. The TFT substrate structure according to the third embodiment of the present invention is a combination formation of a Co-planar structure and a back channel etching (BCE) structure. Specifically, the TFT substrate structure comprises a substrate 1, a first metal layer 31 formed on the substrate 1, a first insulation layer 41 formed on the first metal layer 31, a second metal layer 32 formed on the first insulation layer 41, a first active layer 21 formed on the second metal layer 32 and contact the first insulation layer 41, a second insulation layer 42 formed on the first active layer 21 and the second metal layer 32, and covering the first insulation layer 41, a second active layer 22 formed on the second insulation layer 42, a third metal layer 33 formed on the second active layer 22 and the second insulation layer 42, a passivation layer 6 formed on the second active layer 22 and the third metal layer 33, and covering the second insulation layer 42, and a pixel electrode layer 7 formed on the passivation layer 6 and contacting the third metal layer 33.

(17) Specifically, in this structure, the first metal layer 31 is a gate of a TFT 11, the left side of the second metal layer 32 is a source/a drain of a TFT 11, and the right side is a gate of the TFT 12, i.e. the gate of the TFT 12 and the drain of the TFT 11 are connected. The third metal layer 33 is a source/a drain of the TFT 12.

(18) Significantly, in the TFT substrate shown in FIG. 4, the first TFT 11 employs a formation of the Co-planar structure (Co-planar), and the second TFT 12 employs a formation of the back channel etching (BCE). Similarly, the first TFT 11 can employ a formation of the back channel etching (BCE), while the second TFT 12 employs a formation of the Co-planar structure (Co-planar).

(19) Please refer to FIG. 5. The TFT substrate structure according to the fourth embodiment of the present invention is a combination formation of an etching stopper layer (ESL) and a back channel etching (BCE) structure. Specifically, the TFT substrate structure comprises a substrate 1, a first metal layer 31 formed on the substrate, a first insulation layer 41 formed on the first metal layer 31, and covering the substrate 1 and the first metal layer 41, a first active layer 21 formed on the first insulation layer 41, an etching stopper layer 5 formed on the first active layer 21, a second metal layer 32 formed on the first insulation layer 41 and the etching stopper layer 5, and covering the first active layer 21, a second insulation layer 42 formed on the second metal layer 32, and covering the first insulation layer 41, a second active layer 22 formed on the second insulation layer 42, a third metal layer 33 formed on the second insulation layer 42, and covering two ends of the second active layer 22, a passivation layer 6 formed on the third metal layer 33 and the second active layer 22, and covering the second insulation layer 42, and a pixel electrode layer 7 formed on the passivation layer band contacting the third metal layer 33.

(20) Specifically, in this structure, the first metal layer 31 is a gate of a TFT 11, the left side of the second metal layer 32 is a source/a drain of a TFT 11, and the right side is a gate of the TFT 12, i.e. the gate of the TFT 12 and the drain of the TFT 11 are connected. The third metal layer 33 is a source/a drain of the TFT 12.

(21) Significantly, in the TFT substrate shown in FIG. 5, the first TFT 11 employs a formation of the etching stopper layer (ESL), and the second TFT 12 employs a formation of the back channel etching (BCE). Similarly, the first TFT 11 can employ a formation of the back channel etching (BCE), while the second TFT 12 employs a formation of the etching stopper layer (ESL).

(22) Furthermore, in the aforesaid first to fourth embodiments of the TFT substrate, material of the first active layer 21 and material of the second active layer 22 respectively are amorphous silicon (a-Si) and metal oxide semiconductor, Low Temperature Poly-silicon (LTPS) and amorphous silicon (a-Si), or both metal oxide semiconductor. Besides, in the aforesaid first embodiment, the material of the second active layer 22 respectively can be Low Temperature Poly-silicon (LTPS) and metal oxide semiconductor.

(23) Preferably, material of the oxide semiconductor can be Indium Gallium Zinc Oxide (IGZO).

(24) Please refer to FIG. 6. The TFT substrate structure according to the fifth embodiment of the present invention is a combination formation of a Co-planar structure and a back channel etching (BCE) structure. Specifically, the TFT substrate structure comprises a substrate 1, a first metal layer 31 formed on the substrate 1, a first insulation layer 41 formed on the first metal layer 31, and covering the substrate 1 and the first metal layer 31, a first active layer 21 formed on the first insulation layer 41, a second metal layer 32 formed on two ends of the first active layer 21 and the first insulation layer 41, a second insulation layer 42 formed on the first active layer 21 and the second metal layer 32, and covering the first insulation layer 41, a third metal layer 33 formed on the second insulation layer 42, a second active layer 22 formed on the third metal layer 33 and contacting the second insulation layer 42, a passivation layer 6 formed on the third metal layer 33 and the second active layer 22, and covering the second insulation layer 42, and a pixel electrode layer 7 formed on the passivation layer 6 and contacting the third metal layer 33; the first active layer 21 and the second active layer 22 are at the same side of the substrate 1. By stacking-up deposing the TFTs with different functions, the occupied area of TFTs is diminished and the aperture ratio is increased.

(25) Furthermore, material of the first active layer 21 and material of the second active layer 22 respectively are amorphous silicon (a-Si) and metal oxide semiconductor, or both metal oxide semiconductor. Preferably, material of the oxide semiconductor can be Indium Gallium Zinc Oxide (IGZO).

(26) FIG. 7 shows electric property curve diagrams of the metal oxide semiconductor TFTs of the TFT substrate structure according to the present invention. It verifies that differentiations do exist between the Switching TFT and the Driving TFT in the TFT substrate of the present invention.

(27) In the experiment and verification, both the active layers of the Switching TFT and the Driving TFT employ oxide semiconductor material. By changing the condition parameters of the experiments, the differentiations of the electrical properties of the two are achieved ultimately. Specifically, as shown in FIG. 7, (a) and (b) can realize the differentiation of S.S; (a) and (c) can realize the differentiation of Vth (similar to Vg to realize one TFT on and on TFT off) and also can be applied in other circuits; (a) and (d) can realize the differentiation of Ion. Therefore, the TFT substrate structure of the present invention can differentiate the electrical properties of different TFTs.

(28) In conclusion, the present invention provides a TFT substrate structure. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized. The process is simple. The manufacture cost is low. By stacking-up deposing the TFTs with different functions, the aperture ratio is increased.

(29) Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.