A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction. The first stacked unit includes the charge storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor layer. The second direction intersects the first direction. The second separation film contains silicon.

A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a floating gate is removed by using a spacer insulating film, a first insulating film, and a second insulating film as a mask. A floating gate having a tip portion is formed from the conductive layer for the floating gate, and a part of an insulating layer for a gate insulating film is exposed from the floating gate. The tip portion of the floating gate is further exposed by selectively removing the second insulating film among the second insulating film, the insulating layer for the gate insulating film, and the spacer insulating film.

An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

Provided is a highly integrated semiconductor device which can hold data and includes a NAND cell array. Each of the plurality of memory cells of the NAND cell array includes a first transistor, a second transistor, a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal is electrically connected to one electrode connected to a channel region of the first transistor. The second terminal is electrically connected to the other electrode connected to the channel region of the first transistor. The third terminal is electrically connected to a gate electrode of the second transistor. The fourth terminal is electrically connected to one electrode connected to a channel region of the second transistor. A gate electrode of the first transistor is in contact with the other electrode connected to the channel region of the second transistor. A string of the plurality of memory cells is formed by connecting the first terminals and the second terminals.

A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.