An array substrate, an electro-static discharge method thereof and a display device are disclosed. The array substrate includes: a plurality of data lines, a plurality of gate lines, a power signal line, a charge release signal line, a plurality of electro-static discharge units and at least one short circuit ring unit. The charge release signal line and the power signal line are disposed in parallel, two electro-static discharge units are disposed between them to form an electro-static discharge circuit, each gate line and/or each data line is connected with the charge release signal line by one electro-static discharge unit; the short circuit ring unit is connected between the charge release signal line and the power signal line.

An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

A semiconductor device is provided. The semiconductor device includes an active region, a gate line, a first metal interconnect, a power rail, and a second metal interconnect. The gate line overlaps the active region and extends along a first direction. The first metal interconnect overlaps the active region and the gate line. The first metal interconnect extends along a second direction intersecting the first direction. The power rail is disposed in a higher layer than the first metal interconnect. The power rail extends along the second direction. The second metal interconnect is disposed in a same layer as the power rail, the second metal interconnect extends along the second direction.

The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

The present disclosure provides a method for fabricating an array substrate. The method includes providing a substrate; forming a first pattern on the substrate including a plurality of signal lines and a plurality of electrostatic discharge (ESD) lines, wherein an ESD line is configured to connect two signal lines; and removing a portion of each ESD line during a process for forming a second pattern over the first pattern to disconnect the two signal lines.

A display panel is provided. The display panel has an active area and a border area out of the active area. The display panel includes a plurality of pixels, a first gate driver portion, a plurality of scan lines and a multiplexer portion. The pixels are located in the active area. The first gate driver portion is located in the border area. The scan lines are located in the active area, and connected to the first gate driver portion. The multiplexer portion is located in the border area. The multiplexer portion and the first gate driver portion at least partially overlap along a direction parallel to one of the plurality of scan lines.

A display panel and a display device are provided. The display panel includes an array substrate and an opposite substrate arranged oppositely; a sealant disposed in non-display areas; and a peripheral wiring disposed in the non-display areas of the array substrate and/or the opposite substrate and including at least one electrostatic discharge (ESD) structure.

An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.