A display device comprising a display panel that includes an active area, the active area including a data line positioned on a substrate in a first direction and transferring a data signal, a gate line positioned on the substrate in a second direction and transferring a gate signal, a thin film transistor connected to the gate line and the data line, and a plurality of pixels driven by the thin film transistor, a first pad coupled to a first signal line disposed in a data signal area wherein the first signal line is connected to the data line, and a first non-signal line disposed in a first non-signal area wherein the first non-signal line is disconnected from the data line, the first non-signal area being disposed outside the data signal area, a second pad coupled to a second signal line disposed in a gate signal area wherein the second signal line is connected to the gate line, and a second non-signal line disposed in a second non-signal area wherein the second non-signal line is disconnected from the gate line, the second non-signal area being disposed outside the gate signal area; and a dummy pattern disposed between the data signal area and the first non-signal area, or disposed between the gate signal area and the second non-signal area.

Interconnects (34) include an inside interconnect section (40) and an outside interconnect section (41). The inside interconnect section (40) includes a first interconnect layer (42), a second interconnect layer (43), and a connection section (44) that connects the first interconnect layer (42) and the second interconnect layer (43). The outside interconnect section (41) includes a third interconnect layer (45). Of a plurality of interconnects (34), in one interconnect (X) of neighboring interconnects the second interconnect layer (43) and the third interconnect layer (45) are connected, and in another of the neighboring interconnects (Y), the first interconnect layer (42) and the third interconnect layer (45) are connected.

An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

An integrated circuit package includes an integrated circuit die. The integrated circuit die includes core circuitry implemented in one or more layers of semiconductor material, a first cluster of first contact pads formed of a top metal layer of the integrated circuit die and coupled to the core circuitry, a second cluster of second contact pads formed of the top metal layer and coupled to the core circuitry, a first ESD protection line formed of the top metal layer extending between an area of the first cluster and an area of the second cluster, and ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry. The integrated circuit package includes a passivation layer on the integrated circuit die and a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line.

A semiconductor device according to an embodiment includes a plurality of circuit units each including a substrate, a first electrode on a first side of the substrate, a second electrode aligned with the first electrode on the first side of the substrate, a third electrode on a second side of the substrate, and a first switching element and a second switching element. The switching elements are aligned on the substrate between the first electrode, second electrode and third electrode, electrically connected in series between the first electrode and the second electrode, and having the third electrode electrically connected therebetween. In two of the adjacent circuit units, the first side of one circuit unit and the first side of the other circuit unit are adjacent to each other, and the second side of the one and the second side of the other are adjacent to each other.

An ESD protection device comprising an SCR-type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area of an N-type well. One or more diodes connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers between doped regions instead of gate oxide technology significantly reduces unwanted leakage currents.

A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.

A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail.