A semiconductor device includes a high-voltage semiconductor element with a first doped region of a first conductivity type. The first doped region at least partly laterally surrounds a central portion. The central portion and the first doped region may form an auxiliary junction. A second doped region of a second conductivity type at least partly laterally surrounds the first doped region. A drift region of the first or second conductivity type extends from the first doped region to the second doped region, and forms a first pn junction with the first doped region or the second doped region.

A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.

Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, having a corundum structure, the conductive substrate having a larger area than the oxide semiconductor film.

A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A drain region comprises a well in the base layer, a doped region above and coupled with the well, a first drift region above and coupled with the first region, and a second drift region above the first doped region. The first doped region is at least partially in the insulator layer and the first drift region is at least partially in the semiconductor layer. A trench isolation structure is within the drain region and a gate stack is partially over the semiconductor layer and overlapping the first drift region.

A voltage level shifter includes an input stage with series-connected first and second N-type field effect transistors (NFETs) and an output stage with an inverter connected to an intermediate node between the first and second NFETs. Gates of the first and second NFETs are connected to an output node of the inverter and an input node, respectively. An input voltage signal on the input node toggles between a first voltage and ground. An intermediate voltage signal on the intermediate node toggles between a second voltage (lower than the first voltage) and ground. An output voltage signal on the output node toggles between the second voltage and ground. A capacitor in the input stage is connected between the input and intermediate nodes so that, when the input voltage switches to ground, the intermediate voltage signal is pulled to ground to facilitate switching of the output voltage signal to the second voltage.

The present disclosure introduces an IC apparatus that includes a transistor and circuitry, as well as method of manufacture of such IC apparatus. The transistor is constructed in layers formed in or over a semiconductor substrate and includes a polysilicon member proximate a feature of the transistor. The circuitry includes two connections to the polysilicon member and is configured to detect a temperature-dependent characteristic of the polysilicon member. The transistor may also or instead include oppositely doped portions of the semiconductor substrate, which form a junction diode. The circuitry may also or instead include connections to the oppositely doped substrate portions and may be configured to detect a temperature-dependent characteristic of the junction diode.

A semiconductor device includes a first node having a first conductivity type in a semiconductor layer, a second node having a first region with a second, opposite, conductivity type in the semiconductor layer, and a second region adjacent to the first region in the semiconductor layer, and a minority carrier collector having the first conductivity type in the second region of the second node in the semiconductor layer. Another semiconductor device includes an anode in a semiconductor layer, a cathode spaced apart from the anode in the semiconductor layer, and a minority carrier collector adjacent the cathode in the semiconductor layer and having P-type dopants.

The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device includes a semiconductor substrate, an insulating buried layer, a drift region, and a plurality of dielectric isolation structures. The insulating buried layer is located on the semiconductor substrate. The drift region is located on the insulating buried layer. A drain region is provided on part of the upper surface of the drift region. The plurality of dielectric isolation structures are located in the drift region and on the insulating buried layer, and are spaced apart from each other in a direction towards the drain region. At least one dielectric isolation structure protrudes from the insulating buried layer and is bent towards the drain region.