One embodiment of the present invention relates to a method for manufacturing solar cells having a nano-micro composite structure on a silicon substrate and solar cells manufactured thereby. The technical problem to be solved is to provide a method for manufacturing solar cells and solar cells manufactured thereby, the method being capable of forming micro wires in various sizes according to the lithographic design of a photoresist and forming nano wires, which have various sizes and aspect ratios, by adjusting the concentration of a wet etching solution and immersion time. To this end, the present invention provides a method for manufacturing solar cells and solar cells manufactured thereby, the method comprising the steps of: preparing a first conductive semiconductor substrate having a first surface and a second surface; patterning a photoresist on the second surface of the first conductive semiconductor substrate such that the plane form of the photoresist becomes a form in which multiple horizontal lines and multiple vertical lines intersect each other; electrolessly etching the semiconductor substrate so as to form a micro wire having a width of 1-3 m and a height of 3-5 m in a region corresponding to the photoresist and to form multiple nano wires having a width of 1-100 nm and a height of 1-3 m in a region not corresponding to the photoresist; doping the micro wire and nano wires with a second conductive impurity by using POCl.sub.3; forming a first electrode on the first surface of the semiconductor substrate; and forming a second electrode on the micro wire, wherein the efficiency of the solar cells is 10-13%, the efficiency being the ratio of output to incident light energy per unit area.

A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.

A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.

The present disclosure provides a method of manufacturing a pattern including: forming a trench structure on a substrate using an inkjet method; filling an interior portion of the trench structure with a filler; and removing the trench structure, and a pattern manufactured using the same, and a method of manufacturing a solar battery using the method of manufacturing a pattern and a solar battery manufactured using the same.

A solar cell element comprises a semiconductor substrate, a passivation layer and a protective layer. The semiconductor substrate includes a p-type semiconductor region on one main surface thereof. The passivation layer is located on the p-type semiconductor region and contains aluminum oxide. The protective layer is located on the passivation layer and contains silicon oxide which contains hydrogen and carbon.

A high efficiency configuration for a solar cell module comprises solar cells conductively bonded to each other in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. The front surface metallization patterns on the solar cells may be configured to enable single step stencil printing, which is facilitated by the overlapping configuration of the solar cells in the super cells. A solar photovoltaic system may comprise two or more such high voltage solar cell modules electrically connected in parallel with each other and to an inverter. Solar cell cleaving tools and solar cell cleaving methods apply a vacuum between bottom surfaces of a solar cell wafer and a curved supporting surface to flex the solar cell wafer against the curved supporting surface and thereby cleave the solar cell wafer along one or more previously prepared scribe lines to provide a plurality of solar cells. An advantage of these cleaving tools and cleaving methods is that they need not require physical contact with the upper surfaces of the solar cell wafer. Solar cells are manufactured with reduced carrier recombination losses at edges of the solar cell, e.g., without cleaved edges that promote carrier recombination. The solar cells may have narrow rectangular geometries and may be advantageously employed in shingled (overlapping) arrangements to form super cells.

The present disclosure enables high-volume cost effective production of three-dimensional thin film solar cell (3-D TFSC) substrates. Pyramid-like unit cell structures 16 and 50 enable epitaxial growth through an open pyramidal structure 3-D TFSC embodiments 70, 82, 100, and 110 may be combined as necessary. A basic 3-D TFSC having a substrate, emitter, oxidation on the emitter, and front and back metal contacts allows for simple processing. Other embodiments disclose a selective emitter, selective backside metal contacts, and front-side SiN ARC layers. Several processing methods, including process flows 150, 200, 250, 300, and 350, enable production of these 3-D TFSCs.

A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.

Systems, methods, and apparatus for light collection and conversion to electricity are disclosed herein. The disclosed method involves receiving, by at least one concentrating element (e.g., a lens), light from at least one light source, where the light comprises direct light and diffuse light. The method further involves focusing, by at least one concentrating element, the direct light onto at least one concentrator photovoltaic cell. Also, the method involves passing, by at least one concentrating element, the diffuse light onto at least one solar cell of an array of solar cells arranged on a flat plate, where at least one concentrator photovoltaic cell is bonded on top of at least one of the solar cells in the array. In addition, the method involves collecting, by at least one concentrator photovoltaic cell, the direct light. Further, the method involves collecting, by at least one solar cell, the diffuse light.

The photovoltaic cell includes a silicon substrate, a first passivation layer, a second passivation layer, at least one silicon oxynitride layer, and at least one silicon nitride layer. The second passivation layer includes a first silicon oxide layer and at least one aluminum oxide layer, and a thickness of the at least one aluminum oxide layer is in a range of 4 nm to 20 nm. The number of silicon atoms is greater than the number of oxygen atoms in the at least one silicon oxynitride layer and the number of oxygen atoms is greater than the number of nitride atoms in the at least one silicon oxynitride layer. The first silicon oxide layer is disposed between the substrate and the at least one aluminum oxide layer, and a thickness of the first silicon oxide layer is in a range of 0.1 nm to 5 nm.