A semiconductor structure includes a SiC substrate, a heavily doped SiC layer, an AlGaN epitaxial layer, and a GaN epitaxial layer that are stacked sequentially. The GaN epitaxial layer includes a heavily doped layer and a lightly doped layer that are stacked, and the SiC substrate, the heavily doped SiC layer, the AlGaN epitaxial layer, and the GaN epitaxial layer are all of a first conductivity type. Design of the heavily doped SiC layer in the present disclosure is conducive to reducing on-resistance, so as to achieve a low turn-on voltage.

JFETs are provided that comprise a wide bandgap semiconductor layer structure comprising an active region and a termination region. The termination region comprises a plurality of termination structures. A first major surface of the semiconductor layer structure in the active region comprises a plurality of spaced-apart mesas and the first major surface of the semiconductor layer structure in the termination region is a planar surface.

The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control region the effective doping dose has a higher value than at other points of the substrate doping increase region (2) below the gate electrode.

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

A junction field-effect transistor with asymmetric gates, and a method of making the same. A channel is constructed of semiconductor material, a source is located at a first end of the channel, and a drain is located at a second end. A first gate is located at and extends along a first side of the channel and creates a first depletion region, and a second gate is located at and extends along a second side of the channel and creates a second depletion region. The gates are physically asymmetric with regard to at least one of their relative position along the channel, their relative size, or their relative shape (e.g., one gate may project into the channel toward the other gate). The physical asymmetry of the first and second gates results in their respective depletion regions being asymmetric, which affects the ability to control electrical current flowing through the channel.

A cascade arrangement and to a semiconductor module. The cascode arrangement includes: a substrate, a JFET, a MOSFET, and at least one sensor system. A drain terminal of the MOSFET is electrically connected to a source terminal of the JFET and a source terminal of the MOSFET is electrically connected to a gate terminal of the JFET. A first semiconductor layer in which the MOSFET is formed and a second semiconductor layer in which the JFET is formed, are situated stacked on top of one another via a connecting material. Both an electrical and a thermal coupling between the JFET and the MOSFET are implemented via the connecting material. The stacked semiconductor layers are situated on the substrate. The first semiconductor layer includes a first subarea in which the MOSFET is formed and at least one second subarea in which the at least one sensor system is formed.

A method for manufacturing semiconductor device according to an embodiment includes: forming a first metal oxide layer containing aluminum as a main component above a substrate; forming an oxide semiconductor layer above the first metal oxide layer; forming a gate insulating layer above the oxide semiconductor layer; forming a second metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the second metal oxide layer is formed above the gate insulating layer; removing the second metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.

A SiC semiconductor device includes a substrate of a first conductivity type, a buffer layer of the first conductivity type on the substrate, a low-concentration layer on the buffer layer, a first deep layer and a JFET portion on the low-concentration layer, a current diffusion layer of the first conductivity type disposed on the JFET portion and having an impurity concentration higher than the low-concentration layer, a second deep layer of a second conductivity type disposed on the first deep layer, a base layer of the second conductivity type disposed on the current diffusion layer and the second deep layer, an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, and a trench gate structure penetrating the impurity region and the base layer and reach the current diffusion layer. The JFET portion is formed with defect portions.