A cuttable solar wrap includes a flexible, sheet-like substrate. A photovoltaic grid, having photovoltaic cells or submodules connected in parallel by internal conductors is incorporated into the substrate. The cuttable solar wrap further includes a plurality of spaced-apart power transfer wires protruding from the substrate, each power transfer wire independently configured to incorporate the solar grid into a circuit. This arrangement enables the solar wrap to be cut at any location, producing pieces, such that each piece retains full photovoltaic function and is independently and effectively able to be incorporated into a circuit without further modification.

A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.

Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device 22 includes a first carrier holding layer 48, which is arranged on a lower electrode 47, is in contact with a lower electrode 47 via a first interface 49, and includes majority carriers of one type, and a second carrier holding layer 57, which is arranged on the first carrier holding layer 48, defines a second interface 58 constituting a conduction path to the first carrier holding layer 48, and includes majority carriers of the other type. The first interface 49 has its outline within the outline of the first carrier holding layer 48 when seen in a plan view in a direction that is orthogonal to a surface of the substrate, and the second interface 58 has its outline within the outline of the first carrier holding layer 48 when seen in the plan view.

This solar cell module (1) comprises a plurality of solar cell arrays (11). Each solar cell array (11) includes a plurality of spherical semiconductor elements (20) arranged in a row, at least a pair of bypass diodes (40), and a pair of lead members (14) that connect the plurality of spherical semiconductor elements (20) and the plurality of bypass diodes (40) in parallel. Each of the lead members (14) includes one or plural lead strings (15) to which the plurality of spherical semiconductor elements (20) are electrically connected and having a width less than or equal to the radius of the spherical semiconductor element (20), and plural lead pieces (16) formed integrally with the lead strings (15) at least at both end portions of the lead member (14), on which the bypass diodes (40) are electrically connected in reverse parallel to the spherical semiconductor elements (20), and having width larger than or equal to the width of the bypass diodes (40).

One embodiment of the present invention relates to a method for manufacturing solar cells having a nano-micro composite structure on a silicon substrate and solar cells manufactured thereby. The technical problem to be solved is to provide a method for manufacturing solar cells and solar cells manufactured thereby, the method being capable of forming micro wires in various sizes according to the lithographic design of a photoresist and forming nano wires, which have various sizes and aspect ratios, by adjusting the concentration of a wet etching solution and immersion time. To this end, the present invention provides a method for manufacturing solar cells and solar cells manufactured thereby, the method comprising the steps of: preparing a first conductive semiconductor substrate having a first surface and a second surface; patterning a photoresist on the second surface of the first conductive semiconductor substrate such that the plane form of the photoresist becomes a form in which multiple horizontal lines and multiple vertical lines intersect each other; electrolessly etching the semiconductor substrate so as to form a micro wire having a width of 1-3 m and a height of 3-5 m in a region corresponding to the photoresist and to form multiple nano wires having a width of 1-100 nm and a height of 1-3 m in a region not corresponding to the photoresist; doping the micro wire and nano wires with a second conductive impurity by using POCl.sub.3; forming a first electrode on the first surface of the semiconductor substrate; and forming a second electrode on the micro wire, wherein the efficiency of the solar cells is 10-13%, the efficiency being the ratio of output to incident light energy per unit area.

A high efficiency configuration for a string of solar cells comprises series-connected solar cells arranged in an overlapping shingle pattern. Front and back surface metallization patterns may provide further increases in efficiency.

Systems and methods for electronic devices are presented. A device includes a substrate. An Indium Gallium Nitride (InGaN) nanoring is formed over the substrate. The InGaN nanoring includes an alloy of Indium Nitride (InN) and Gallium Nitride (GaN). The alloy includes at least 6 percent Indium. A GaN layer may be formed over the InGaN nanoring, and a first electrode is formed over the GaN layer. In one embodiment, the alloy includes less than about 70 percent Indium.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material.

A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.