A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.

A semiconductor device includes a substrate, a first well region of the first conductivity type, and a second well region of the second conductivity type. The semiconductor device also includes a drain region, a source region, and a gate structure. The drain region of the first conductivity type is formed in the first well region and the source region of the first conductivity type is formed in the second well region. The gate structure on the substrate includes the first gate stack near the source region and the second gate stack near the drain region. The first gate stack includes the first gate dielectric layer and the first gate electrode layer. The second gate stack includes the second gate dielectric layer and the second gate electrode layer. The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

Proposed are a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same seeking to improve on-resistance (Rsp) characteristics of the device by forming a field plate on a substrate and above a gate region, and prevent deterioration of HE-SOA characteristics by forming a thin film-shaped gate field plate below the gate region to mitigate an electric field concentrated below the field plate and on an edge of the gate region.

An integrated chip includes a gate structure overlying a substrate between a source region and a drain region. A field plate is disposed within a first dielectric layer overlying the substrate. The field plate is laterally offset from the gate structure by a non-zero distance in a direction towards the drain region. An isolation structure is disposed within the substrate. The field plate directly overlies at least a portion of the isolation structure.

A semiconductor device includes a semiconductor layer over a semiconductor substrate with a body region and a drain drift region of opposite first and second conductivity types, a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region, a gate electrode over the gate dielectric layer, a drain region having the second conductivity type in the drain drift region, the drain region having a dopant density greater than a dopant density of the drain drift region, a field relief dielectric layer over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than the gate dielectric layer, and a floating field plate over the field relief dielectric layer and between the gate electrode and the drain, the field plate spaced apart from the gate electrode.

Semiconductor devices and methods for forming the same are provided. The methods include providing a substrate having source and drain structures separated by body and drift regions, a gate structure between the source and drain structures, an ILD layer over the source, drain, and gate structures, and a source contact coupled to the source structure. The methods include forming a first row of contact field plate (CFP) contacts in the ILD layer between the gate and drain structures, and forming a BEOL structure that is disposed on the ILD layer that includes a conductive metal layer coupled to the first row of CFP contacts and/or to the source structure. The method includes forming at least a second row of CFP contacts in the ILD layer between the gate structure and the drain structure, and/or electrically isolating the CFP contacts from the source structure.

A high voltage semiconductor device and a method of manufacturing the same seek to prevent breakdown voltage characteristics of the device from deteriorating by blocking the formation of an impurity doped region within a substrate due to a separation space between a gate region and a dummy gate region during a subsequent process by overlapping gate spacers between the gate region and the dummy gate region.

A position of an upper surface of a lead-out portion of a gate electrode is higher than an upper surface of an active portion of the gate electrode. An insulating film has a first raised portion positioned on a side surface of the active portion of the gate electrode via a sidewall spacer and a second raised portion positioned on a side surface of the lead-out portion of the gate electrode via the sidewall spacer. An active portion of a field plate electrode is in contact with the first raised portion, and a position of an uppermost portion of the lead-out portion of the field plate electrode is lower than a position of an uppermost portion of the insulating film positioned over the upper surface of the lead-out portion of the gate electrode.

A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

Fabrication method for a SiC integrated circuit which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.