A semiconductor device includes a semiconductor substrate including a corrugated surface. A body has a first conductivity type and includes a portion extending continuously along the corrugated surface. A gate dielectric layer is on the body and extends continuously along the corrugated surface. A gate is on the gate dielectric layer, the gate extending continuously along the corrugated surface. A corrugated conformal drift region has a second conductivity type opposite from the first conductivity type, and is on and conformal with the corrugated surface of the semiconductor substrate, and extends continuously along the corrugated surface. A source has the second conductivity type and includes a portion extending continuously along the corrugated surface, the source being in contact with the body. A drain contact region electrically coupled to the drift region and having the second conductivity type.

Disclosed herein is a method including receiving a semiconductor substrate having a first semiconductor material layer and a different second semiconductor material layer disposed on the first semiconductor material layer, forming a drift region overlapping the first semiconductor material layer, the drift region doped to a first conductivity type, forming a gate electrode layer over the field relief insulator, removing a first portion of the second semiconductor material layer to form a trench that exposes a first portion of the first semiconductor material layer, removing the exposed first portion of the first semiconductor material layer to extend the trench under the gate electrode layer toward the drift region, wherein a second portion of the second semiconductor material layer is exposed in the extended trench, and forming a dielectric isolation structure in the extended trench, the dielectric isolation structure touching the second portion of the second semiconductor material layer.

A power semiconductor device according to example embodiments of the present disclosure may include: a substrate including SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a drain region of the first conductivity type spaced apart inwardly from an edge of the well region by a first length and disposed in the well region; a JFET region of the first conductivity type on the drift layer outside of the well region; a gate electrode extending along an upper surface of the well region and having a ring shape, the gate electrode being disposed on the upper surface of the well region; a source electrode connected to the JFET region; and a drain electrode connected to the drain region.

An LDMOS includes a semiconductor substrate. The semiconductor substrate includes a fin structure and a planar substrate. The fin structure extends from the planar substrate. A gate electrode covers the planar substrate and the fin structure. A first gate dielectric layer is disposed between the gate electrode and the planar substrate. A second gate dielectric layer is between the gate electrode and the fin structure and between the gate electrode and the planar substrate. The first gate dielectric layer is connected to the second gate dielectric layer. A source is disposed in the fin structure at one side of the gate electrode and a drain is disposed in the planar structure at the other side of the gate electrode.

Disclosed is a high voltage semiconductor device. More particularly, a high voltage semiconductor device is disclosed, including a slope compensating structure on at least a portion of an outermost surface of a gate spacer defining a sidewall of a gate structure, thereby reducing or preventing electric field concentration in a corner of a gate field plate, and thus improving reliability of the device.