In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.

Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.

A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron gas in the first layer, a source electrode provided on the second layer, a drain electrode provided on the second layer, a gate electrode provided between the source electrode and the drain electrode on the second layer, and a first insulating layer provided between the gate electrode and the drain electrode on the second layer, the first insulating layer being a first oxide of at least one first element selected from the group consisting of Hf, Zr, Ti, Al, La, Y, and Sc, the first insulating layer containing 510.sup.19 cm.sup.3 or more of at least one second element selected from the group consisting of F, H, D, V, Nb, and Ta.

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into on and off states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches.

A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface.

A semiconductor device and a method of making the same. The device includes a substrate having an AlGaN layer located on one or more GaN layers, for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a source contact. The device further includes a drain contact. The device also includes a gate contact located between the source contact and the drain contact. The gate contact includes a gate electrode. The gate contact also includes an electrically insulating layer located between the gate electrode and the AlGaN layer. The insulating layer includes at least one aperture for allowing holes generated during an off-state of the device to exit the device through the gate electrode.

A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron gas in the first layer; a source electrode provided on the second layer, a drain electrode provided on the second layer, a gate electrode provided between the source electrode and the drain electrode on the second layer and a first insulating layer provided between the gate electrode and the drain electrode on the second layer. The first insulating layer includes a first film, a second film having a higher oxygen density than the first film and a first region provided between the first film and the second film. The first region contains at least one first element selected from the group consisting of F, H, and D, the first region having a first peak of concentration of the first element.