A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.

A dual-gate device can control display pixels, such as LED-based pixels. The dual-gate device can include two thin-film transistors (TFTs). A first TFT or top gate structure can be deposited directly on a second TFT or bottom gate structure. The first TFT can include a first conducting layer, a first gate insulator, and a semiconductor structure. The semiconductor structure can include a source and a drain. The second TFT can include the semiconductor structure, a second gate insulator, and a second conducting layer. By stacking the first TFT on top of the second TFT, a fabrication process can involve fewer masks and less expense than processes that involve forming the two TFTs separately or on separate portions of a substrate.

A display panel includes a substrate, a mark structure, a plurality of active elements, and a plurality of light emitting elements. The mark structure is disposed in a mark region of the display panel. The mark structure includes a drilled layer having a plurality of through holes. The active elements are disposed in an active element region of the display panel. Both the mark region and the active element region are located in a display region of the display panel. The light emitting elements are disposed in the display region of the display panel. A first portion in the light emitting elements is overlapped with the mark structure in a normal direction of a surface of the substrate.

A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

A thin film transistor and a display device comprising the same is disclosed. The thin film transistor comprises an active layer on a substrate, and a first gate electrode at least partially overlapped with the active layer, wherein the active layer includes a channel portion, a first connection portion that is in contact with one side of the channel portion, and a second connection portion that is in contact with the other side of the channel portion, and an effective gate voltage applied to a first area of the channel portion, which is in contact with the first connection portion, is greater than that applied to a second area of the channel portion, which is in contact with the second connection portion.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first conductive layer with the first insulating layer therebetween. The second insulating layer covers the top surface and a side surface of the second conductive layer. The third conductive layer is positioned over the second insulating layer. The semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second insulating layer, and the third conductive layer. The third insulating layer is positioned over the semiconductor layer. The fourth conductive layer is positioned over the semiconductor layer with the third insulating layer therebetween.

A semiconductor device includes an isolation structure over a substrate, a fin-shaped base protruding from the substrate and through the isolation structure, channel members vertically stacked above the fin-shaped base, first and second dielectric fins over the isolation structure and sandwiching the channel members, an epitaxial feature atop the fin-shaped base and abutting the channel members, a gate structure wrapping around at least one of the channel members, and a gate spacer extending along a sidewall of the gate structure. Bottom surfaces of the first and second dielectric fins are above a top surface of the isolation structure. An interface between the epitaxial feature and the fin-shaped base is above the top surface of the isolation structure.

The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.

Disclosed is a method of fabricating an oxide semiconductor thin-film transistor, the method including a step of forming an oxide semiconductor layer including a channel region, a source region, and a drain region on a substrate; a step of forming a gate insulating layer on the channel region; a step of forming a gate electrode on the gate insulating layer; and a step of forming a source electrode and a drain electrode on the source and drain regions, respectively, wherein the step of forming an oxide semiconductor layer includes a step of selectively plasma-treating the source and drain regions of the oxide semiconductor layer with a fluorine (F)-based gas, and the source and drain regions contain fluorine (F) at a concentration of 210.sup.14/cm.sup.3 to 17.510.sup.21/cm.sup.3.

Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.