A thin film transistor, a thin film transistor substrate including the thin film transistor and a display device are provided. The thin film transistor includes a first active layer, a first auxiliary gate electrode and a first gate electrode, wherein the first active layer includes a first channel portion, a first connection portion that is in contact with one side of the first channel portion, and a second connection portion that is in contact with the other side of the first channel portion.

An integrated circuit device including a plurality of gate stacks disposed on a substrate and including a first gate stack and a second gate stack, a spacer disposed on sidewalls of each of the plurality of gate stacks, a plurality of source/drain areas disposed in an upper portion of the substrate and at sides of the plurality of gate stacks, an active area disposed in the upper portion of the substrate and between adjacent source/drain areas of the plurality of source/drain areas, a channel semiconductor layer disposed between the active area and the second gate stack among the plurality of gate stacks.

A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

Systems, methods and apparatus are provided for a two access device, one storage node memory cell in a vertical three-dimensional memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. The memory cell has a second horizontally oriented access device having a first source/drain region and a second source/drain region separated by a second channel region. The second access device is operatively controlled by a second gate. A shared storage node is coupled between the second source/drain regions of the first access device and the second access device.

According to various example embodiments, a semiconductor element includes: a channel layer including a semiconductor material; a p-type semiconductor layer and an n-type semiconductor layer apart from each other with the channel layer therebetween, a paraelectric layer on a first area of the channel layer, a ferroelectric layer on a second area different from the first area of the channel area, and having a polarization state due to a voltage applied from an external source, a first gate electrode on the paraelectric layer, a second gate electrode on the ferroelectric layer, and an insulating layer between the first gate electrode and the second gate electrode, and electrically separating the first gate electrode and the second gate electrode from each other.

A semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and first to fourth wirings. The first transistor includes a first gate and a second gate, and one of a source and a drain of the first transistor is connected to the first wiring and the second gate, and the other of the source and the drain is connected to one of a source and a drain of the second transistor and one electrode of the capacitor. A gate of the second transistor is connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring. The first wiring is supplied with a first potential, and the second wiring is supplied with a second potential and a third potential alternately. The third wiring is connected to the first gate and supplied with a first signal. The fourth wiring is connected to the gate of the second transistor and supplied with a second signal obtained by inverting the first signal.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

A memory device includes: a substrate; and a seven-transistor memory cell including: a first fin and a second fin, where the first fin is narrower than the second fin; a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, where the second and third gate structures are between the first and the fourth gate structures, where the fourth and the fifth gate structures extend along a same line, where in a top view, the first and the fourth gate structures overlap the first fin, the second and the third gate structures overlap the first and the second fins, and the fifth gate structure overlaps the second fin; p-type source/drain regions over the first fin; and n-type source/drain regions over the second fin.

Disclosed is a TFET with an OR-AND logic function. By arranging a horizontal channel and a vertical channel in different directions, three gates are not connected and will not be affected by each other, and can control the current of a whole channel jointly; when a first gate and a second gate are both at a high level, the TFET will be turned on, and when the first gate and a third gate are both at a high level, the TFET will also be turned on; the horizontal channel not only isolates the second gate from the third gate, but also reduces the strength of coupling between the second gate and the third gate, so only a small current passes through the horizontal channel when the second gate and the third gate are both at a high level, and the TFET will not be turned on at this moment.