As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

An array substrate, a driving method thereof and a display device are disclosed. In the array substrate, one second scanning signal line is disposed at a position corresponding to the (2N+1)th row of sub-pixels or the (2N+2)th row of sub-pixels, or one second scanning signal line is disposed at a position corresponding to the (N+1)th row of sub-pixels; each first switching element is disposed in a corresponding sub-pixel; each second switching element is disposed in a corresponding sub-pixel group; each first scanning signal line is configured to control a plurality of first switching elements in one row of sub-pixels; and each second scanning signal line is configured to control a plurality of second switching elements in one row of sub-pixel groups. The display device can have resolution reduced by half or three fourth in the case of full screen display, and lowers drive power consumption of the display panel without affecting display brightness.

An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

A display device includes a substrate, a first insulating layer having a first side wall, an oxide semiconductor layer on the first side wall, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer, a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.

To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate uses a connection semiconductor (42) that is formed in a semiconductor layer and is subjected to N-type heavy doping to connect a first semiconductor (41) and a second semiconductor (43) so as to connect the first TFT and the second TFT in series. The N-type heavily doped connection semiconductor (42) substitutes a connection electrode that is formed in a second metal layer in prior art techniques for preventing the design rules of the connection electrode and the second metal layer from being narrowed due to the connection electrode being collectively present on the second metal layer with signal lines of a data line and a voltage supply line and for facilitating increase of an aperture ratio and definition of a display panel. The present invention also provides a TFT substrate structure, which has a simple structure and possesses a high aperture ratio and high definition.

A method for forming a semiconductor device includes forming a fin device structure in a buffer layer on a substrate. The fin device structure includes a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion. The method also includes forming a sacrificial layer disposed over the fin device structure and forming a device semiconductor layer disposed over a surface of the sacrificial layer. A gate dielectric layer is then formed and is disposed over a surface of the device semiconductor layer. A gate electrode layer is formed and disposed over a surface of the gate dielectric layer. The method includes removing a portion of the sacrificial layer to form a cavity surrounding the fin structure and performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure.