P-Si TFT and method for fabricating the same, array substrate and method for fabricating the same, and display device

Abstract

A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

Claims

1. A method for fabricating a Polysilicon Thin-Film Transistor (P-Si TFT), said method comprising: forming a polysilicon active layer; forming a first gate insulation layer and a first gate electrode sequentially on the active layer, wherein a projection of the first gate electrode is located between first and second ends of the active layer; conducting a first ion implantation process on the active layer using the first gate electrode as a mask to form a doped region at each of the first and second ends of the active layer; forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, wherein a projection of each end of the second gate electrode is located between the projection of the first electrode and a respective end of the active layer; and conducting a second ion implantation process on the active layer by using the second gate electrode as an additional mask to form two source/drain implantation regions at two outer sides of the two doped regions of the active layer, wherein an impurity concentration of the doped regions is smaller than that of the source/drain implantation regions.

2. The method according to claim 1, wherein an amount of ions implanted by the first ion implantation process is lower than an amount of ions implanted by the second ion implantation process.

3. The method according to claim 1, wherein: the amount of ions implanted by the first ion implantation process is within a range of 110.sup.12110.sup.14 atoms/cm.sup.3; and the amount of ions implanted by the second ion implantation process is within a range of 110.sup.14110.sup.18 atoms/cm.sup.3.

4. A method for fabricating an array substrate, said method comprising: providing a base substrate; and forming Polysilicon Thin-Film Transistors (P-Si TFTs) according to claim 1 on the base substrate.

5. The method according to claim 4, further comprising: forming a storage capacitor bottom electrode on the first gate insulation layer corresponding to a predetermined storage capacitor region; and forming a storage capacitor top electrode on the second gate insulation layer corresponding to the storage capacitor bottom electrode.

6. The method according to claim 5, wherein the storage capacitor bottom electrode and the first gate electrode are formed simultaneously, and wherein the storage capacitor top electrode and the second gate electrode are formed simultaneously.

7. The method according to claim 5, further comprising: forming a buffer layer on the base substrate, subsequent to providing the base substrate and prior to forming the polysilicon active layer.

8. The method according to claim 7, wherein the buffer layer is made of silica, silicon nitride, or a laminate thereof.

9. A Polysilicon Thin-Film Transistor (P-Si TFT) comprising: a polysilicon active layer that includes a center region, two doped regions arranged at each of the first and second ends of the center region, and two source/drain implantation regions arranged at respective outer sides of the two doped regions; a first gate insulation layer and a first gate electrode arranged on the active layer, wherein a projection of each end of the first gate electrode coincides with a respective end of the center region; and a second gate insulation layer and a second gate electrode arranged on the first gate insulation layer and the first gate electrode, wherein a projection at each end of the second gate electrode coincides with a respective end of the two doped regions, and wherein an impurity concentration of the doped regions is smaller than that of the source/drain implantation regions.

10. The P-Si TFT according to claim 9, wherein a thickness of the active layer is within a certain range of 100 3000 .

11. The P-Si TFT according to claim 9, wherein at least one of the first gate insulation layer and the second gate insulation layer is made of at least one of silica, silicon nitride, and a laminate thereof, and wherein a thickness thereof is within a certain range of 500 2000 .

12. The P-Si TFT according to claim 9, wherein at least one of the first gate electrode and the second gate electrode is made of at least one of metal and metal alloy, and wherein a thickness thereof is within a certain range of 1000 5000 .

13. An array substrate comprising: a base substrate; and Polysilicon Thin-Film Transistors (P-Si TFTs) according to claim 9 arranged on the base substrate.

14. The array substrate according to claim 13, further comprising: storage capacitors, wherein each storage capacitor includes a storage capacitor bottom electrode formed on the first gate insulation layer and a storage capacitor top electrode formed on the second gate insulation layer.

15. The array substrate according to claim 13, further comprising: a buffer layer arranged between the base substrate and the polysilicon active layer.

16. The array substrate according to claim 15, wherein the buffer layer is made of silica, silicon nitride, or a laminate thereof.

17. A display device comprising: the array substrate according to claim 13.

18. A display device comprising the array substrate according to claim 14.

19. A display device comprising the array substrate according to claim 15.

20. A display device comprising the array substrate according to claim 16.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to illustrate the technical solutions of the present disclosure or the related art in a more apparent manner, the drawings desired for the embodiments of the present disclosure will be described briefly hereinafter. The following drawings merely relate to some embodiments of the present disclosure, and based on these drawings, a person skilled in the art may obtain the other drawings without any creative effort.

(2) FIG. 1 is a schematic diagram illustrating a structure of a Thin-Film Transistor (TFT) according to the related art;

(3) FIG. 2 is a flow chart illustrating a method for fabricating a Polysilicon Thin-Film Transistor (P-Si TFT) according to a certain embodiment of the present disclosure;

(4) FIG. 3 is a flow chart illustrating a method for fabricating an array substrate according to a certain embodiment of the present disclosure;

(5) FIG. 4 is a flow chart illustrating a method for fabricating a display device according to a certain embodiment of the present disclosure;

(6) FIG. 5 is a schematic diagram illustrating an active layer that is formed according to a certain embodiment of the present disclosure;

(7) FIG. 6 is a schematic diagram illustrating a first gate insulation layer, a first gate electrode, and a storage capacitor bottom electrode that are formed according to a certain embodiment of the present disclosure;

(8) FIG. 7 is a schematic diagram illustrating a first ion implantation process according to a certain embodiment of the present disclosure;

(9) FIG. 8 is a schematic diagram illustrating a second gate insulation layer, a second gate electrode, and a storage capacitor top electrode that are formed according to a certain embodiment of the present disclosure;

(10) FIG. 9 is a schematic diagram illustrating a second ion implantation process according to a certain embodiment of the present disclosure; and

(11) FIG. 10 is a schematic diagram illustrating a structure of an array substrate according to a certain embodiment of the present disclosure.

DETAILED DESCRIPTION

(12) In order to make the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. The following embodiments are merely a part of, rather than all of, the embodiments of the present disclosure. Based on these embodiments, a person skilled in the art may obtain the other embodiments, which also fall within the scope of the present disclosure.

(13) Such words as first and second used in the specification and claims are merely used to differentiate different components rather than to represent any order, number, or importance. It is well known in the art that forming respective layers indicates sputtering and depositing respective layers of materials, and one or more patterning processes on the materials, such as an etching process, may be needed if necessary. A sequence of steps of any methods provided by embodiments of the present disclosure is not only limited to the one described in the specification, but some of steps can be re-adjusted in sequence or can concurrently happen.

(14) As used herein and in the appended claims, the singular form of a word includes the plural, and vice versa, unless the context clearly dictates otherwise. Thus, the references a, an, and the are generally inclusive of the plurals of the respective terms. Likewise, the terms include, including, and having should all be construed to be inclusive of features, integrals, steps, operations, elements, and/or parts, unless such features, integrals, steps, operations, elements, and/or parts are clearly prohibited from the context, which does not exclude one or more other features, integrals, steps, operations, elements, and/or parts from the present disclosure.

(15) As shown in FIG. 2, which is a flow chart illustrating a method for fabricating a Polysilicon Thin-Film Transistor (P-Si TFT) according to a certain embodiment of the present disclosure, the method includes:

(16) Step 201, forming a polysilicon active layer;

(17) Step 202, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, wherein a projection of the first gate electrode (i.e., a projection of the first gate electrode on the active layer) locates between two edges at both ends of the active layer;

(18) Step 203, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask, so as to form two doped regions at both ends of the active layer;

(19) Step 204, forming a second gate insulation layer and a second gate electrode sequentially on the resultant first gate insulation layer and the resultant first gate electrode, wherein projections of two edges at both ends of the second gate electrode locate between the projection of the first electrode and two edges at both ends of the active layer, respectively; and

(20) Step 205, conducting a second ion implantation process on the active layer by using the second gate electrode as another mask, so as to form two source/drain implantation regions at two outer sides of the two doped regions of the active layer.

(21) Specifically, due to the fact that there is one gate insulation layer and two gate insulation layers with respect to the first and second ion implantation processes, an amount of ions implanted by the first ion implantation process is lower than that of ions implanted by the second ion implantation process. Alternatively, the amount of ions implanted by the first ion implantation process is within a range of 110.sup.12110.sup.14 atoms/cm3, while the amount of ions implanted by the second ion implantation process is within a range of 110.sup.12110.sup.18 atoms/cm3. Also, subsequent to the second ion implantation process, because impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions, the two doped regions may be referred to as lightly doped regions.

(22) As shown in FIG. 3, which is a flow chart illustrating a method for fabricating an array substrate according to a certain embodiment of the present disclosure, the method includes:

(23) Step 301, providing a base substrate;

(24) Step 302, forming the above described P-Si TFTs on the base substrate.

(25) Specifically, the method may include a step for fabricating a storage capacitor region, which further includes forming a storage capacitor bottom electrode on the first gate insulation layer corresponding to a predetermined storage capacitor region and forming a storage capacitor top electrode on the second gate insulation layer corresponding to the storage capacitor bottom electrode.

(26) Specifically, the storage capacitor bottom electrode and the first gate electrode are formed simultaneously, while the storage capacitor top electrode and the second gate electrode are formed simultaneously.

(27) Moreover, in order to prevent metal ion impurity in the base substrate from diffusing into the active layer to adversely affect the working performance of the TFT, a buffer layer may be formed on the base substrate, which may be made of silica, silicon nitride, or a laminate thereof.

(28) Further, embodiments of the present disclosure also provide a method for fabricating an array substrate. As shown in FIG. 4, the method includes steps 401405.

(29) In step 401, a base substrate is provided, and P-Si TFTs are formed on the base substrate.

(30) As shown in FIG. 5, in step 401, the base substrate 1 may be a transparent substrate, such as cleansed glass in advance. A buffer layer may be formed on the base substrate 1, which may be made of silica, silicon nitride, or a laminate thereof, so as to prevent metal ion impurity in the base substrate from diffusing into the active layer to adversely affect the working performance of the TFT. The P-Si active layer 2 formed on the base substrate 1 may derive from an a-Si layer, formed under 600 degrees or below, by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a Low-Pressure Chemical Vapor Deposition (LPCVD) process, or a sputtering process. Then the a-Si layer may be converted into a P-Si layer by an Excimer Laser Annealing (ELA) process, a Metal Induced Crystallization (MIC) process, or a Solid Phase Crystallization (SPC) process. It needs to be appreciated that, according to different crystallization processes used, specific process procedures and a structure of the array substrate may be different to some extent. Although technical effects achieved by different embodiments of the present disclosure can be realized, one or more additional processes may be incorporated into the fabricating procedure, such as a heat treatment dehydrogenation process, a deposition induced metal process, a heat treatment crystallization process, an excimer laser irradiation crystallization process, a doping process (P-type doping or N-type doping) on the source/drain regions, and a doped impurity activation process. Specifically, a thickness of the active layer 2 is within a certain range of 100 angstroms ()3000 . In a certain embodiment, a thickness of the active layer 2 is within a certain range of 500 1000 .

(31) In step 402, a first gate insulation layer and a first gate electrode are formed sequentially on the active layer, and a storage capacitor bottom electrode is formed on the first gate insulation layer corresponding to a predetermined storage capacitor region. And a projection of the first gate electrode on the active layer locates between two edges at both ends of the active layer.

(32) As shown in FIG. 6, in step 402, the first gate insulation layer 3 is first formed on the active layer 2. Subsequently, the first gate electrode 4 and the storage capacitor bottom electrode 6 are formed on the resultant first gate insulation layer 3. Further, a projection of the first gate electrode 4 on the active layer 2 locates between two edges at both ends of the active layer 2.

(33) In step 403, a first ion implantation process is conducted on the active layer by using the first gate electrode as a mask, so as to form two doped regions at two ends of the active layer.

(34) As shown in FIG. 7, two doped regions 8 are formed at two ends of the active layer 2, by conducting an ion implantation process using the first gate electrode 4 as a mask.

(35) In step 404, a second gate insulation layer and a second gate electrode are formed sequentially on the first gate insulation layer and the first gate electrode, while a storage capacitor top electrode is formed on the second gate insulation layer corresponding to the storage capacitor bottom electrode. The projections of two edges at both ends of the second gate electrode locate between the projection of the first electrode and two edges at both ends of the active layer, respectively.

(36) As shown in FIG. 8, in step 404, the second gate insulation layer 5 is formed on the first gate insulation layer 3, the first gate electrode 4, and the storage capacitor bottom electrode 6. Subsequently, the second gate electrode 9 and the storage capacitor top electrode 7 are formed. Projections of two edges at both ends of the second gate electrode 9 locate between the projection of the first electrode 4 and two edges at both ends of the active layer 2, respectively.

(37) In step 405, a second ion implantation process is conducted on the active layer by using the second gate electrode as another mask, so as to form two source/drain implantation regions at outer sides of the two doped regions of the active layer.

(38) As shown in FIG. 9, in step 405, a second ion implantation process is conducted on the active layer 2 by using the second gate electrode 9 as another mask, so as to form two source/drain implantation regions 10 at two outer sides of the two doped regions 8 of the active layer 2.

(39) Specifically, the first gate insulation layer 3 and the second gate insulation layer 5 may be a single layer of silica, or a single layer of silicon nitride, or a laminate thereof. The first gate insulation layer 3 and the second gate insulation layer 5 may be obtained by a PECVD process, a LPCVD process, an Atmospheric-Pressure Chemical Vapor Deposition (APCVD) process, or an Electron-Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) process. A thickness of the first gate insulation layer 3 and the second gate insulation layer 5 may be within a certain range of 500 2000 and can be determined according to actual design needs. In a certain embodiment, a thickness of the first gate insulation layer 3 and the second gate insulation layer 5 may be within a certain range of 600 1500 . Further, the first gate electrode 4 and the second gate electrode 9 as well as the storage capacitor bottom electrode 6 and the storage capacitor top electrode 7 may be of a single layer, double layers, or a structure having more than two layers. The first gate electrode 4 and the second gate electrode 9 as well as the storage capacitor bottom electrode 6 and the storage capacitor top electrode 7 may be made of metal or metal alloy, such as molybdenum (Mo), aluminum (Al), molybdenum tungsten (MoW). A thickness of the first gate electrode 4 and the second gate electrode 9 as well as the storage capacitor bottom electrode 6 and the storage capacitor top electrode 7 may be within a certain range of 1000 5000 . In a certain embodiment, a thickness of the first gate electrode 4 and the second gate electrode 9 as well as the storage capacitor bottom electrode 6 and the storage capacitor top electrode 7 may be within a certain range of 1500 4000 . Accordingly, the first gate electrode 4 and the second gate electrode 9 as well as the storage capacitor bottom electrode 6 and the storage capacitor top electrode 7 constitute gate electrodes of the TFT and masks for ion implantation processes on the left, as well as the upper and lower electrodes of the storage capacitor on the right, as shown in FIG. 9.

(40) The first and second ion implantation processes may choose from a group of an ion implantation process with a mass analyzer, an ion cloud implantation process without a mass analyzer, a plasma implantation process, and a solid state diffusion implantation process. In some embodiments of the present disclosure, a prevailing ion cloud implantation process has been adopted. Specifically, mixed air including borate material such as B.sub.2H.sub.6/H.sub.2 and phosphorated material such as PH3/H2 may be implanted according to actual design needs. Specifically, energy for ion implantation may be within a range of 10200 keV. In a certain embodiment, energy for ion implantation may be within a range of 40100 keV. Due to the fact that there is one gate insulation layer and two gate insulation layers arranged respectively, lower energy for the first ion implantation process and higher energy for the second ion implantation process are adopted. The amount of ions implanted by the ion implantation processes is within a range of 110.sup.11110.sup.20 atoms/cm3. Specifically, the first ion implantation process is called as a Lightly Doped Drain (LDD) implantation process, which needs a lower amount of ions implantation. In a certain embodiment, the amount of ions implanted by the first ion implantation process is within a range of 110.sup.12110.sup.14 atoms/cm3. The second ion implantation process is called as a source/drain implantation process, which needs a higher amount of ions implantation. In a certain embodiment, the amount of ions implanted by the second ion implantation process is within a range of 110.sup.14110.sup.18 atoms/cm3.

(41) Further, subsequent to the above steps, a source electrode and a drain electrode need to be formed on the second gate electrode 9, and are connected with the source/drain implantation regions 10 through via-holes respectively.

(42) As shown in FIG. 10, embodiments of the present disclosure provide a P-Si TFT, which includes a polysilicon active layer 2 that includes a center region, two doped regions 8 arranged at two outer sides of the center region respectively, and two source/drain implantation regions 10 arranged at two outer sides of the two doped regions 8 respectively, a first gate insulation layer 3 and a first gate electrode 4 arranged on the active layer 2, wherein projections of two edges at both ends of the first gate electrode 4 coincide with those of two edges at both ends of the center region respectively, and a second gate insulation layer 5 and a second gate electrode 9 arranged on the first gate insulation layer 3 and the first gate electrode 4, wherein projections of two edges at both ends of the second gate electrode 9 coincide with those of two edges at two outermost ends of the two lightly doped regions 8 respectively.

(43) Specifically, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions. As a result, the two doped regions are also referred to as lightly doped regions. Further, a thickness of the active layer 2 is within a certain range of 100 3000 . In a certain embodiment, a thickness of the active layer 2 is within a certain range of 500 1000 .

(44) Specifically, the first gate insulation layer 3 and/or the second gate insulation layer 5 is/are made of a single layer of silica, a single layer of silicon nitride, or a laminate thereof. Further, a thickness of the first gate insulation layer 3 and/or the second gate insulation layer 5 is within a certain range of 500 2000 . In a certain embodiment, a thickness of the first gate insulation layer 3 and/or the second gate insulation layer 5 is within a certain range of 600 1500 .

(45) Specifically, the first gate electrode 4 and/or the second gate electrode 9 is made of metal and/or metal alloy, such as molybdenum (Mo), aluminum (Al), molybdenum tungsten (MoW). Further, a thickness of the first gate electrode 4 and/or the second gate electrode 9 is within a certain range of 1000 5000 . In a certain embodiment, a thickness of the first gate electrode 4 and/or the second gate electrode 9 is within a certain range of 1500 4000 . It can be appreciated that a P-Si TFT may achieve its good performance according to the above material and size thereof, for example.

(46) As shown in FIG. 10, embodiments of the present disclosure also provide an array substrate, which includes a base substrate 1, and the above described P-Si TFTs arranged on the base substrate 1.

(47) Specifically, the array substrate may further include storage capacitors each including a storage capacitor bottom electrode 6 formed on the first gate insulation layer 3 and a storage capacitor top electrode 7 formed on the second gate insulation layer 5.

(48) Specifically, the array substrate may further include a buffer layer (not shown) arranged between the base substrate 1 and the polysilicon active layer 2.

(49) Further, embodiments of the present disclosure provide a display device, which includes the above described array substrate.

(50) The display device may be any product or component with a display function, such as a display panel, a screen, a TV, a tablet, a mobile phone, a navigator, etc.

(51) According to the P-Si TFT and the method for fabricating the same, the array substrate for fabricating the same, and a display device provided by embodiments of the present disclosure, there is no need for an additional mask used solely for forming LDD regions, but rather a good-quality TFT having LDD regions and a storage capacitor are formed simultaneously with the first and second gate electrodes as ion implantation masks, by adjusting procedures of ion implantation processes and a corresponding gate electrode structure. Accordingly, due to the fact that there are lightly-doped and high-resistance LDD regions for a TFT, it can therefore reduce leakage electricity thereof and improve stability thereof, with the process complexity unchanged.

(52) The above are merely example embodiments of the present disclosure and shall not be used to limit the scope of the present disclosure. It should be noted that, a person skilled in the art may make improvements, substitutions and modifications without departing from the principle of the present disclosure, and these improvements, substitutions and modifications shall also fall within the scope of the present disclosure.