Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.

A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.

A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface.

An imaging device with excellent imaging performance is provided. In the imaging device, a first layer, a second layer, and a third layer have a region overlapping with one another, the first layer and the second layer each include transistors, and the third layer includes a photoelectric conversion element. Off-state currents of the transistors formed in the first layer are lower than those of the transistors formed in the second layer, and field-effect mobilities of the transistors formed in the second layer are higher than those of the transistors formed in the first layer.

A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

A dual gate oxide semiconductor thin-film transistor (TFT) substrate includes a substrate; a bottom gate positioned on the substrate; a bottom gate isolation layer positioned on the substrate and the bottom gate; a first oxide semiconductor layer positioned on the bottom gate isolation layer above the bottom gate; an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first oxide semiconductor layer; a top gate isolation layer positioned on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate isolation layer; a top gate positioned on the top gate isolation layer above a middle part of the first oxide semiconductor layer; a source and a drain positioned on the top gate isolation layer at two sides of the top gate; and a passivation layer positioned on the top gate isolation layer, the source, the drain, and the top gate.

The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.