The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.

An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate electrode line and a common electrode line, an insulation layer, a drain electrode and a source electrode, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. The bottom transparent conductive layer, the protection layer, and the top transparent conductive layer are sequentially stacked on the planarization layer. The patternized poly-silicon layer includes a first portion and a second portion. The drain electrode includes an extension section extending therefrom and opposite to the second portion.

Provided are a display apparatus and a manufacturing method of the same. The display apparatus includes: a counter substrate, and an active matrix substrate including a pixel area. The active matrix substrate includes, in a non-transmissive region of each pixel, a transparent substrate, a polycrystalline silicon film, a gate insulating film, a gate electrode, an interlayer insulating film, and a drain layer including patterned conductive films, and includes, in a transparent region of each pixel, the transparent substrate, the gate insulating film and the interlayer insulating film. The interlayer insulating film includes zones where the interlayer insulating film is thinner than a part of the interlayer insulating film at the middle of each transmissive region. The zones are each located so as to extend between the neighboring patterned conductive films and are further located so as not to overlap with the transmissive regions and regions laid over LDD portions of the polycrystalline silicon film.

A device includes a substrate; a light blocking layer on the substrate; a passivation film covering the light blocking layer on the substrate; a thin film transistor on the passivation film; another passivation film covering the thin film transistor; a color filter on the another passivation film; and an insulation layer on the another passivation film and covering the color filter, wherein the light blocking layer is patterned using a composition including a heat resistance polymer, a cross-linking agent, a black colorant, and a solvent. A method of patterning the light blocking layer is also provided.

Discussed is a display device, that may include a substrate divided into a display area and a non-display area except the display area, a first light shielding film formed in the display area, a second light shielding film formed in the non-display area, and oxide thin film transistors and organic light emitting diodes, which are formed on the first light shielding film, wherein the first light shielding film and the second light shielding film are spaced apart from each other.

An active device of a pixel structure includes a semiconductor layer, an insulation layer covering the semiconductor layer, a gate electrode disposed on the insulation layer and electrically connected to a scan line, a protection layer covering the gate electrode, a source electrode and a drain electrode electrically connected to a source region and a drain region of the semiconductor layer. A channel region is disposed between the source region and the drain region. A source lightly doped region is disposed between the channel region and the source region. A drain lightly doped region is disposed between the channel region and the drain region. The light shielding pattern shields the source lightly doped region and the drain lightly doped region. The light shielding pattern is overlapped with one side of the scan line and not overlapped with another side of the scan line.

An array substrate is provided. The array substrate includes: a substrate; a LTPS TFT disposed above the substrate; a planarization layer covering the LTPS TFT; a via hole formed in the planarization layer, wherein the via hole reveals a drain electrode of the LTPS TFT; multiple common electrodes and receiving electrodes disposed separately on the planarization layer, wherein the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other; a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole. A manufacturing method for the array substrate is also provided. The present invention can reduce one manufacturing process and decrease production cost.

The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate according to the present invention forms a gate electrode in the same metal layer with source and drain electrodes and divides a common electrode layer that is conventionally in the form of an entire surface into two portions, of which one serves as a common electrode, while the other portion feeds an input of a gate scan signal thereby eliminating an operation of forming an interlayer insulation layer and thus reducing manufacturing cost of the operation. The array substrate of the present invention comprises a gate electrode that is formed in the same metal layer with source and drain electrodes so that no interlayer insulation layer is present between the gate electrode and the source and drain electrodes, thereby simplifying the structure and reducing the manufacturing cost of the array substrate.

An object of the present invention is to provide a small-sized active matrix type liquid crystal display device that may achieve large-sized display, high precision, high resolution and multi-gray scales. According to the present invention, gray scale display is performed by combining time ratio gray scale and voltage gray scale in a liquid crystal display device which performs display in OCB mode. In doing so, one frame is divided into subframes corresponding to the number of bit for the time ratio gray scale. Initialize voltage is applied onto the liquid crystal upon display of a subframe.

A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions.