An AMOLED back plate includes a substrate on which a buffer layer and a poly-silicon section are sequentially formed. A source and a drain are respectively formed of P-type heavy doped micro silicon on the poly-silicon section that have edges facing and spaced from each other to define a channel therebetween. A gate isolation layer is formed on the buffer layer, the source, the drain and the channel. A gate is formed on the gate isolation layer and has opposite edges that face in directions toward the edges of the source and the drain. The opposite edges of the gate are spaced from the edges of the source and the drain by predetermined spacing distance in horizontal directions so as to prevent the gate from overlapping the source and the drain.

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region is separated from the first semiconductor region in a first direction. The third semiconductor region is provided between the first and the second semiconductor regions. The third conductor is separated from the third semiconductor region in a second direction intersecting the first direction. The third semiconductor region includes first and second partial regions. The first partial region includes a first metal element, and is amorphous. The second partial region is stacked with the first partial region in the second direction, and is polycrystalline. A first concentration of the first metal element in the first partial region is higher than a second concentration of the first metal element in the second partial region, or the second partial region does not include the first metal element.

A method for forming contact silicide for a semiconductor structure. In one embodiment, a dielectric layer is formed over a p-type region of a semiconductor structure comprising a gate stack and source and drain regions. The source and drain regions are formed within a semiconductor layer. First and second contact trenches are formed within the dielectric layer exposing at least a portion of the source region and a portion of the drain region, respectively. First and second metal layers are formed within the first and second contact trenches. The second metal layer includes a metallic material that is different from a metallic material of the first meal layer. The metallic materials of the first and second metal layers in a lower region of the first and second contact trenches are intermixed. A silicide is formed within the source and drain regions from the semiconductor layer and the intermixed metallic materials.

In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

The present invention provides a manufacture method of an AMOLED back plate and a structure thereof. The manufacture method of the AMOLED back plate is: sequentially deposing a buffer layer (2), an amorphous silicon layer (2) on a substrate (1), and crystallizing and converting the amorphous silicon layer to be a polysilicon layer, and patterning the polysilicon layer, and then deposing a P type heavy doped micro silicon layer (P+uc-Si), and implementing a photo process to define a position of a channel (40), and etching the P type heavy doped micro silicon layer (P+uc-Si) to form a source/a drain (41), and thereafter, sequentially forming a gate isolation layer (5), a gate (61), an interlayer insulation layer (7), a metal source/a metal drain (81), a flat layer (9), an anode (10), a pixel definition layer (11) and a photo spacer (12); the source/the drain (41) and the gate (61) do not overlap in the horizontal direction and are mutually spaced. The method can improve the electrical property of the drive TFT to make the conductive current higher, and the leakage current lower, and diminish the image sticking for raising the display quality of the AMOLED.

An array substrate for a liquid crystal display (LCD) device include: a substrate; a gate line formed in one direction on one surface of the substrate; a data line crossing the gate line to define a pixel area; a thin film transistor (TFT) configured at a crossing of the gate line and the data line; a pixel electrode formed at a pixel region of the substrate; an insulating film formed on the entire surface of the substrate including the pixel electrode and the TFT, including a first insulating film formed of a high temperature silicon nitride film and a second insulating film formed of a low temperature silicon nitride film, and having a contact hole having an undercut shape exposing the pixel electrode; a pixel electrode connection pattern formed within the contact hole having an undercut shape and connected with the pixel electrode and the TFT; and a plurality of common electrodes separately formed on the insulating film.

The invention relates to a method for fabricating an array substrate, an array substrate and a display device. The method for fabricating an array substrate may comprise: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound. By converting only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line into a metal semiconductor compound, the resulting metal semiconductor compound may prevent oxidative-corrosion of the metal thin film layer, such as a low-resistance metal (e.g., Cu or Ti) layer, in the subsequent procedures, which is favorable for the fabrication of a metal oxide thin film transistor using Cu or Ti.