METHOD FOR FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

Abstract

The invention relates to a method for fabricating an array substrate, an array substrate and a display device. The method for fabricating an array substrate may comprise: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound. By converting only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line into a metal semiconductor compound, the resulting metal semiconductor compound may prevent oxidative-corrosion of the metal thin film layer, such as a low-resistance metal (e.g., Cu or Ti) layer, in the subsequent procedures, which is favorable for the fabrication of a metal oxide thin film transistor using Cu or Ti.

Claims

1-17. (canceled)

18. A method for fabricating an array substrate, comprising: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound.

19. The method according to claim 18, further comprising: prior to forming the pattern including the source electrode, drain electrode and data line, forming on the substrate a gate, a gate line, a gate insulation layer covering the gate and the gate line, and an active layer arranged on the gate insulation layer and corresponding to the gate.

20. The method according to claim 19, wherein the step of forming a pattern including a source electrode, a drain electrode and a data line comprises: forming a metal thin film layer; and removing the metal thin film layer outside regions of the source electrode, drain electrode and data line through a patterning process.

21. The method according to claim 20, further comprising: removing the non-crystalline semiconductor thin film layer outside the regions of the source electrode, drain electrode and data line.

22. The method according to claim 21, further comprising: forming a passivation layer, and etching portions of the passivation layer corresponding to the drain electrode, gate line and data line to form corresponding through-holes.

23. The method according to claim 22, further comprising: forming a via-hole of the gate insulation layer at a position corresponding to the gate line on the gate insulation layer.

24. The method according to claim 23, further comprising: forming a transparent conductive thin film and forming a pattern including a pixel electrode, a connection line for the gate line and a connection line for the data line on the passivation layer with the through-holes through a patterning process, wherein a metal semiconductor compound on the drain electrode is electrically connected to the pixel electrode by means of the through-hole corresponding to the drain electrode.

25. The method according to claim 3, wherein the metal thin film layer comprises a layer of copper or titanium.

26. The method according to claim 21, wherein the metal thin film layer comprises a layer of copper or titanium.

27. The method according to claim 22, wherein the metal thin film layer comprises a layer of copper or titanium.

28. The method according to claim 23, wherein the metal thin film layer comprises a layer of copper or titanium.

29. The method according to claim 18, wherein the non-crystalline semiconductor thin film layer comprises a layer of -silicon, -germanium, -gallium arsenide, -arsenic sulfide or -selenium.

30. The method according to claim 18, wherein the metal semiconductor compound comprises a silicide of copper, a germanide of copper, a compound of copper and -gallium arsenide, a compound of copper and -arsenic sulfide, a compound of copper and -selenium, a silicide of titanium, a germanide of titanium, a compound of titanium and -gallium arsenide, a compound of titanium and -arsenic sulfide, or a compound of titanium and -selenium.

31. The method according to claim 18, wherein the thickness of the non-crystalline semiconductor thin film layer is 10 -50 .

32. The method according to claim 18, wherein a temperature for the annealing ranges between 200 C. and 280 C.

33. The method according to claim 18, wherein the annealing is performed under nitrogen atmosphere.

34. The method according to claim 19, wherein the active layer is a metal oxide layer.

35. The method according to claim 36, wherein the metal oxide layer comprises an indium gallium zinc oxide, indium tin zinc oxide or nitrogen-doped zinc oxide semiconductor layer.

36. An array substrate, fabricated by a method, wherein the method comprises: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound.

37. A display device comprising an array substrate fabricated by a method, wherein the method comprises: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0027] FIG. 2 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0028] FIG. 3 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0029] FIG. 4 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0030] FIG. 5 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0031] FIG. 6 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0032] FIG. 7 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0033] FIG. 8 illustrates a step of the method for fabricating an array substrate according to an embodiment of the invention.

[0034] The following reference signs will be used throughout the drawings: [0035] 12: a substrate; 14: a gate; 16: a gate line; 18: a gate insulation layer; [0036] 20: an active layer; 22a: a source electrode; 22b: a drain electrode; [0037] 22c: a data line; 24: a non-crystalline semiconductor thin film layer; [0038] 26a: a source metal semiconductor compound layer; [0039] 26b: a drain metal semiconductor compound layer; [0040] 26c: a metal semiconductor compound layer for the data line; [0041] 30: a passivation layer; [0042] 32a: a through-hole corresponding to the drain electrode; [0043] 32b: a through-hole corresponding to the gate line; [0044] 32c: a through-hole corresponding to the data line; [0045] 34: a pixel electrode; 36: a connection line for the gate line; [0046] 38: a connection line for the data line.

DETAILED DESCRIPTION OF THE INVENTION

[0047] Embodiments of the invention will be described in detail below with reference to FIGS. 1-8 of the application.

[0048] The term forming mentioned herein shall be understood in a broad sense. For example, it can be performed by means of processes commonly used in the art, such as chemical vapor deposition and molecular beam epitaxy, and so on. Since there are many ways for forming thin films and there are relatively more suitable formation processes for different materials, technical processes for forming each thin film will not be specifically indicated herein, as these processes are not the key points of the invention.

[0049] FIGS. 1-8 illustratively show the steps of the method for fabricating an array substrate according to an embodiment of the invention. Firstly, forming a gate 14 and a gate line 16 on a substrate 12 such as a silicon substrate. The gate line 16 may be used to connect the gates 14 of various transistors in the subsequent procedures. That is to say, prior to forming a metal thin film layer for a source electrode, a drain electrode and a data line, the gate 14 and the gate line 16 are formed on the substrate 12. As for the metal thin film layer for the source electrode, the drain electrode and the data line, it will be further expounded hereinafter.

[0050] Next, as shown in FIG. 2, a gate insulation layer 18 may be formed on the gate 14, the gate line 16 and remaining portions of the substrate 12 not covered by the gate 14 and the gate line 16, i.e., the gate insulation layer 18 at least covering the gate 14 and gate line 16 is formed. An active layer 20 may be formed on the gate insulation layer 18, which is also above the region of the gate 14, i.e., the active layer 20 arranged on the gate insulation layer 18 and corresponding to the region of gate 14 may be formed. The active layer 20 may be a metal oxide layer, for example, indium gallium zinc oxide InGaZnO (IGZO), indium tin zinc oxide InSnZnO (ITZO), nitrogen-doped zinc oxide ZnON, or a semiconductor layer such as non-crystalline silicon (-silicon).

[0051] Subsequently, a pattern including a source electrode, a drain electrode and a data line may be formed. As shown in FIG. 3, a source electrode 22a, a drain electrode 22b and a data line 22c may be formed at corresponding positions of the gate insulation layer 18 and the active layer 20. The steps of forming a pattern including a source electrode, a drain electrode and a data line may comprise forming a metal thin film layer. The complete metal thin film layer is not shown in FIG. 3. For convenience of fabrication, the metal thin film layer may cover the entire region of the active layer 20 and the (exposed) upper surface of the gate insulation layer 18 not occupied by the active layer 20. Then, the metal thin film layer outside regions of the source electrode, drain electrode and data line may be removed by a patterning process. In FIG. 3, the metal thin film layer outside regions of the source electrode, drain electrode and data line has been removed by a patterning process, and only portions of the metal thin film layer for the source electrode 22a, the drain electrode 22b and the data line 22c are remained. The metal thin film layer may be a copper or titanium layer. Alternatively, the metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c can be also directly formed, and the patterning process could be omitted in this way.

[0052] Subsequently, a non-crystalline semiconductor thin film layer 24 may be formed, as shown in FIG. 4. For convenience of fabrication, the non-crystalline semiconductor thin film layer 24 may be formed on the metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c, the exposed upper surface of the gate insulation layer 18 and the upper surface of the active layer 20. In this embodiment, this is only for convenience of the formation of the non-crystalline semiconductor thin film layer 24. Alternatively, non-crystalline semiconductor thin film layers 24 can be also directly formed only on the metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c. The non-crystalline semiconductor thin film layer 24 may be a layer of -silicon, -germanium, -gallium arsenide, -arsenic sulfide or -selenium. In an embodiment, the thickness of the non-crystalline semiconductor thin film layer 24 may be 10 -50 .

[0053] Then, an annealing process may be performed, so as to only convert the non-crystalline semiconductor thin film layer 24 on the source electrode, drain electrode and data line to a metal semiconductor compound, as shown in FIG. 5, for example, a source metal semiconductor compound layer 26a, a drain metal semiconductor compound layer 26b and a metal semiconductor compound layer 26c for the data line shown in FIG. 5. Only the non-crystalline semiconductor thin film layers 24 on the source electrode, drain electrode and data line are converted into a metal semiconductor compound, while non-crystalline semiconductor thin film layers 24 at other positions are not converted into the metal semiconductor compound. This is because the non-crystalline semiconductor thin film layer 24 such as -silicon may react with the metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c below to form corresponding metal semiconductor compound, whereas the non-crystalline semiconductor thin film layer 24 such as -silicon at other positions does not react with the gate insulation layer 18 or active layer 20 below. In this embodiment, the gate insulation layer 18 may be made of a low-permittivity non-crystalline fluorinated resin or a high-permittivity metal oxide (e.g., SiO.sub.2) or the like. These materials of the gate insulation layer 18 would not react with the non-crystalline semiconductor thin film layer 24 such as -silicon above during the annealing process. Likewise, the active layer (e.g., IGZO, ITZO or ZnON, etc.) would not react with the non-crystalline semiconductor thin film layer 24 above such as -silicon, either. On the contrary, the non-crystalline semiconductor thin film layer 24 of -silicon would react with the metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c below. During the annealing process, Cu atoms in the metal thin film layer (e.g., a Cu layer) for the source electrode 22a, drain electrode 22b and data line 22c would diffuse into the non-crystalline semiconductor thin film layer 24 (e.g., an -silicon layer), such that Cu atoms and Si atoms bind together to form a silicide of copper, such as Cu.sub.5Si. There is a strong binding force between Cu and Si. The adhesion of Cu.sub.5Si is very strong such that the binding between Cu and oxygen can be prevented. Accordingly, the problem of oxidative-corrosion for Cu may be mitigated or avoided. The annealing process may be performed under nitrogen atmosphere, so as to form a thicker silicide of copper, for example, Cu.sub.5Si. In an embodiment, annealing may be performed at a temperature ranging about between 200 C. and 280 C.

[0054] According to an embodiment of the invention, metal semiconductor compounds, for example, the source metal semiconductor compound layer 26a, the drain metal semiconductor compound layer 26b and the metal semiconductor compound layer 26c for the data line may include a silicide of copper, a germanide of copper, a compound of copper and -gallium arsenide, a compound of copper and -arsenic sulfide, a compound of copper and -selenium, a silicide of titanium, a germanide of titanium, a compound of titanium and -gallium arsenide, a compound of titanium and -arsenic sulfide, or a compound of titanium and -selenium. It is known to a person skilled in the art that the term denotes an amorphous state.

[0055] The metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c may also be a titanium (Ti) layer. In this case, during the annealing process, Ti atoms in the Ti layer would diffuse into the non-crystalline semiconductor thin film layer 24 such as an -silicon layer, such that Ti atoms and Si atoms bind together to form a silicide of titanium, for example, titanium silicide TiSi.sub.2. Likewise, there is a strong binding force between Ti and Si. The adhesion of TiSi.sub.2 is very strong such that the binding between Ti and oxygen can be prevented, thereby the problem of corrosion for Ti caused by oxidation can be overcomed. In an embodiment, the annealing process may be performed under nitrogen atmosphere, so as to form a thicker silicide of titanium, for example, TiSi.sub.2.

[0056] Since the metal thin film layer for the source electrode 22a, drain electrode 22b and data line 22c may be a layer of copper or titanium, the non-crystalline semiconductor thin film layer 24 may be a layer of -silicon, -germanium, -gallium arsenide, -arsenic sulfide or -selenium, accordingly, the source metal semiconductor compound layer 26a, the drain metal semiconductor compound layer 26b and the metal semiconductor compound layer 26c for the data line formed after annealing may be a silicide of copper, a germanide of copper, a compound of copper and -gallium arsenide, a compound of copper and -arsenic sulfide, a compound of copper and -selenium, a silicide of titanium, a germanide of titanium, a compound of titanium and -gallium arsenide, a compound of titanium and -arsenic sulfide, or a compound of titanium and -selenium. As mentioned above, this is not difficult for a person having ordinary skill in the art to understand.

[0057] Then, the non-crystalline semiconductor thin film layer 24 outside the source electrode, drain electrode and data line may be removed, as shown in FIG. 6. In FIG. 6, after the non-crystalline semiconductor thin film layer 24 outside the source electrode, drain electrode and data line is removed, at least a portion of the active layer 20 and gate insulation layer 18 are exposed.

[0058] Subsequently, a passivation layer 30 may be formed, and portions of the passivation layer 30 corresponding to the drain electrode, gate line and data line may be etched to form corresponding through-holes, for example, through-holes 32a, 32b and 32c respectively located at the positions corresponding to the drain electrode, gate line and data line, as shown in FIG. 7. In an embodiment, a via-hole of gate insulation layer may be formed at a position corresponding to the gate line in the gate insulation layer 18. As can be seen from FIG. 7, the through-hole 32b corresponding to gate line may pass through the passivation layer 30 and the gate insulation layer 18, thus directly exposing the gate line 16.

[0059] After planarization for the passivation layer 30, a transparent conductive thin film may be formed. A pattern including a pixel electrode 34, a connection line 36 for the gate line and a connection line 38 for the data line may be formed on the passivation layer with the through-holes may be formed through a patterning process, and the drain metal semiconductor compound layer 26b may be electrically connected to the pixel electrode 34 by means of the through-hole corresponding to the drain electrode.

[0060] With the method for fabricating an array substrate provided by the embodiments of the invention, by converting only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line into a metal semiconductor compound, the resulting metal semiconductor compound may prevent oxidative-corrosion of the surface of the metal thin film layer (e.g., a Cu or Ti layer) in the subsequent procedures. By means of such method, metal oxide thin film transistors may be fabricated, and also the oxidation of Cu or Ti at the source electrode or drain electrode can be prevented during the fabrication procedure of the thin film transistor using Cu or Ti.

[0061] According to a second aspect of the invention, an array substrate fabricated by using the above mentioned method for fabricating an array substrate is provided.

[0062] As to the array substrate fabricated by using the above mentioned method for fabricating an array substrate, only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line is converted into a metal semiconductor compound, in this way, the resulting metal semiconductor compound may prevent the oxidative-corrosion of the surface of the metal thin film layer, such as a Cu or Ti layer, in the subsequent procedures.

[0063] According to a third aspect of the invention, a display device comprising the above mentioned array substrate is provided.

[0064] Although the invention has been illustrated with reference to embodiments presently considered, it shall be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims. The scope of the appended claims accords with the broadest explanations so as to include each modification as such as well as equivalent structures and functions.