A method of fabricating a thin film transistor including following steps is provided. Sequentially form a semiconductor layer, a metal layer and an auxiliary layer on a substrate. Perform a crystallization process to transform the semiconductor layer into an active layer after the metal layer and the auxiliary layer are disposed on the semiconductor layer. After the active layer is formed, pattern the metal layer to form a source and a drain. Form a gate insulator and a gate. The gate insulator is disposed between the gate and the source and drain.

Embodiments of the invention provide a conductive structure, a thin film transistor, an array substrate, and a display device. The conductive structure comprises a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer. The multilayer conductive structure according to an embodiment of the invention can prevent exterior ions from diffusing into a copper layer and prevent copper ions from diffusing outward to reduce ions diffusion that adversely impacts the electricity performance and chemical corrosion resistance of the copper metal layer, and meanwhile can enhance adhesiveness of the conductive structure, which may be helpful for etching/patterning of the multilayer conductive structure.

The present invention provides a method for manufacturing an AMOLED backplane, in which after a first metal layer is patternized to form a first gate terminal (61), a second gate terminal (63), and an electrode plate (65), with the patternized first metal layer as a shielding layer, a patternized polysilicon layer is subjected to N-type light doping; and then, an insulation layer (7) is deposited and the insulation layer (7) is subjected to non-isotropic etching to form spacers (71), and with patternized first metal layer and the spacers (71) as a shielding layer, the patternized polysilicon layer is subjected to N-type heavy doping to form light-doping drain areas (N) exactly below the spacers (71) on the opposite sides of the first gate terminal (61), whereby light-doping drain areas (N) on opposite sides of a channel area of a switching TFT are made symmetric to each other and the length of the light-doping drain areas (N) is shorten; a conduction current is increased; a photoelectric current can be effectively reduced; one photo mask can be saved; and the cost can be lowered down.

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.

A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.

An electronic device display may have an array of pixel circuits. Each pixel circuit may include an organic light-emitting diode and a drive transistor. Each drive transistor may be adjusted to control how much current flows through the organic light-emitting diode. Each pixel circuit may include one or more additional transistors such as switching transistors and a storage capacitor. Semiconducting oxide transistors and silicon transistors may be used in forming the transistors of the pixel circuits. The storage capacitors and the transistors may be formed using metal layers, semiconductor structures, and dielectric layers. Some of the layers may be removed along the edge of the display to facilitate bending. The dielectric layers may have a stepped profile that allows data lines in the array to be stepped down towards the surface of the substrate as the data lines extend into an inactive edge region.

A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

A display apparatus includes a pixel having a first area emitting light and a second area transmitting light. A pixel circuit unit is in the first area and includes a thin film transistor. An inorganic insulation layer is in the second area. A first insulation layer covers the pixel circuit unit in the first area, and has an opening exposing the inorganic insulation layer in the second area. A first electrode is on the first insulation layer in the first area. The first electrode is electrically connected to the pixel circuit unit. A second insulation layer covers edges of the first electrode and is outside the opening formed in the first insulation layer. A second electrode is in the first area. An intermediate layer, including an emissive layer, is between the first electrode and the second electrode.

A method includes depositing a first metal layer on a native SiO.sub.2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO.sub.2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.