Thin film transistor array substrate and a thin film transistor which comprise a conductive structure comprising a blocking layer and a diffusion prevention layer

Abstract

Embodiments of the invention provide a conductive structure, a thin film transistor, an array substrate, and a display device. The conductive structure comprises a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer. The multilayer conductive structure according to an embodiment of the invention can prevent exterior ions from diffusing into a copper layer and prevent copper ions from diffusing outward to reduce ions diffusion that adversely impacts the electricity performance and chemical corrosion resistance of the copper metal layer, and meanwhile can enhance adhesiveness of the conductive structure, which may be helpful for etching/patterning of the multilayer conductive structure.

Claims

1. A thin film transistor comprising a gate electrode, a source electrode and a drain electrode, at least one of which employ a conductive structure comprising: a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer, wherein a material of the blocking layer is molybdenum alloy which is any one or a mixture of more than two of MoNb, MoW, MoTi and MoZr, and a material of the diffusion prevention layer is molybdenum.

2. The thin film transistor of claim 1, wherein an atom percentage of element(s) except Mo in the molybdenum alloy is between 0.001 at % and 50 at %.

3. The thin film transistor of claim 1, wherein a thickness of the blocking layer is 50 to 1000 , and a thickness of the diffusion prevention layer is 30 to 200 .

4. A thin film transistor array substrate comprising: a substrate; a thin film transistor array, gate lines and data lines formed on the substrate, the thin film transistor array comprising a plurality of thin film transistor each of which comprises a gate electrode, a source electrode and a drain electrode; and pixel electrodes formed in pixel regions defined by the gate lines and the date lines intersecting the gate lines; wherein at least one of the data lines, the source electrodes, the gate lines, the gate electrodes and the drain electrodes employs a conductive structure comprising: a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer, wherein a material of the blocking layer is molybdenum alloy which is any one or a mixture of more than two of MoNb, MoW, MoTi and MoZr, and a material of the diffusion prevention layer is molybdenum.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to clearly illustrate the technical solution of the embodiments of the invention, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the invention and thus are not limitative of the invention.

(2) FIG. 1 is a schematic structural view of a conductive structure provided in an embodiment of the invention; and

(3) FIG. 2 is a schematic structural view of a thin film transistor array substrate provided in an embodiment of the invention.

REFERENCE NUMERALS

(4) 1Substrate; 2aa blocking layer; 2b - - - a diffusion prevention layer 2c - - - a copper layer; 5 - - - a gate electrode; 6 - - - a gate insulation layer; 7 - - - an intrinsic semiconductor layer; 8 - - - an contact semiconductor layer; 9a - - - a data line; 9b - - - a source electrode; 9c - - - a drain electrode; 10 - - - a protection layer; 11 - - - a pixel electrode; 12 - - - a via hole; 13 - - - a substrate.

DETAILED DESCRIPTION

(5) In order to make objects, technical details and advantages of the embodiments of the invention apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the invention. Apparently, the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.

(6) An embodiment of the invention does not employ a copper conductive structure only but employs a multilayer conductive structure to decrease or avoid copper ions of a copper layer from diffusing outwardly and decrease or avoid exterior ions from diffusing to the copper layer due to high diffusivity of copper ions. The multilayer conductive structure of the embodiment of the invention can also overcome the problem that a current copper conductive structure has relatively low adhesiveness to an insulation substrate (for example, a glass substrate or a semiconductor layer) and thus are easy to come off.

(7) An embodiment of the invention provides a multilayer conductive structure, which may be reliably patterned to form a proper lateral profile.

(8) As shown in FIG. 1, the conductive structure comprises a copper layer 2c formed of copper or copper alloy, a blocking layer 2a for blocking copper ions of the copper layer 2c from diffusing outwardly, and a diffusion prevention layer 2b for blocking exterior ions from diffusing to the copper layer 2c and disposed between the copper layer 2c and the blocking layer 2a.

(9) In the aforesaid structure, the blocking layer 2a may be formed on a substrate 1. The substrate 1 may be a base substrate, such as a glass substrate, a quartz substrate, a plastic substrate and so on, and may also be one or several films on an electronic component, such as a gate insulation layer, a semiconductor layer, a passivation layer of a thin film transistor or the like. Other intermediate film layers such as a buffer layer and so on may also be formed between the substrate 1 and the blocking layer 2a. The substrate 1 may be in a single-layer structure, and may also be a structure having two or more layers. The substrate 1 may concurrently comprise different regions of an electronic device, for example, the blocking layer 2a may be concurrently formed on an active layer and a gate insulation layer (that is, the active layer together with the gate insulation layer form the substrate 1) when a drain electrode of an array substrate is made by employing the conductive structure.

(10) The thickness of each layer is determined by a required interface state and an etching status when the above conductive structure is applied to a thin film transistor. For example, the thickness of the blocking layer 2a may be 50 to 1000 , and the thickness of the diffusion prevention layer 2b may be 30 to 200 , and the thickness of the copper layer 2c may be 1000 to 5000 .

(11) The diffusion prevention layer 2b can block exterior ions (such as ions in the blocking layer 2a or in the substrate 1) from diffusing into the copper layer 2c with the above structure to ensure the conductive property and chemical corrosion resistance of the copper layer; meanwhile, the copper ions in the copper layer 2c may also be blocked by the blocking layer 2a and thus are hard to diffuse into the substrate 1 so that an influence to the substrate 1 can be reduced or avoided.

(12) In the present embodiment, a material of the blocking layer 2a is molybdenum alloy as a preferred example. The molybdenum alloy may be any one of MoNb, MoW, MoTi and MoZr, and may also be a mixture consisting of two or more material from the above materials.

(13) The blocking layer 2a employing molybdenum alloy has good adhesiveness to the substrate 1 (such as a base substrate or a semiconductor layer), which can enhance adhesion between the substrate 1 and the conductive structure and thus can improve stability between the conductive structure and the substrate 1; the blocking layer 2a can also prevent copper ions from diffusing into the substrate 1, and exhibits a similar etch selectivity to the diffusion prevention layer 2b and the copper layer 2c, which is helpful for etching them simultaneously during an etching/a patterning process for a multi-layered structure.

(14) In the present embodiment, when the blocking layer 2a is formed of a molybdenum alloy, elements in the molybdenum alloy except Mo is for example between 0.001 at % to 50 at %. For example, when the molybdenum alloy is MoNb, the atom percentage of Nb in the molybdenum alloy is between 0.001 at % to 50 at %, and when the molybdenum alloy is MoNb and MoTi, Nb and Ti in the molybdenum alloy is between 0.001 at % to 50 at % together.

(15) In order to prevent metallic ions in the blocking layer 2a from diffusing to the copper layer 2c, which may in turn result in deterioration of the electricity performance and chemical corrosion resistance of the copper layer 2c, in the above configuration a diffusion prevention layer 2b is further deposited between the blocking layer 2a and the copper layer 2c. The diffusion prevention layer 2b has a material of a crystal structure similar to that of the blocking layer 2a and that of the copper layer 2c, which can ensure adhesiveness at the interface between the blocking layer 2a and the diffusion prevention layer 2b and at the interface between the diffusion prevention layer 2b and the copper layer 2c, and also has an etching selectivity similar to that of the blocking layer 2a and that of the copper layer 2c. For example, a diffusion prevention material is molybdenum (Mo) in a cubic-centered crystal structure, which has a similar crystal structure to the molybdenum alloy (for example MoNb) and belongs to the same isometric system together as copper with a face-centered cubic crystal structure, thus good interfacial performance can be ensured. The conductive structure formed by the above method has good interfacial characteristic and etching property, and the multilayer conductive structure can be reliably patterned during a patterning process so as to form a good lateral profile. The blocking layer may contact with the other film layers when the conductive structure is applied to a specific electronic device, and here the diffusion prevention layer 2b may also prevent metallic ions in the other film layers in contact with the blocking layer from diffusing to the copper layer 2c.

(16) The conductive structure of the embodiment can reduce or avoid the copper layer 2c from being eroded and oxidized, and can be closely attached to the substrate, and also can effectively overcome a problem that the electricity performance and chemical corrosion resistance of the copper layer is deteriorated because metallic ions or other impurities diffuse into the copper layer.

(17) Correspondingly, the present embodiment also provides a method for manufacturing a conductive structure as shown in FIG. 1, and the method comprises the following steps.

(18) Firstly, a blocking layer 2a is formed on a substrate 1 to block copper ions from diffusing to the substrate, and then a diffusion prevention layer 2b is formed on the blocking layer 2a to block ions from diffusing upwardly through the blocking layer, and thereafter, a copper layer 2c is formed of copper or copper alloy on the diffusion prevention layer 2b.

(19) Here, all of the blocking layer 2a, the diffusion prevention layer 2b and the copper layer 2c may be formed by a sputtering process. For example, the blocking layer 2a is formed by employing molybdenum alloy as a sputtering source, the diffusion prevention layer 2b is formed by employing molybdenum as a sputtering source, and the copper layer 2c is formed by employing copper or copper alloy as a sputtering source. The material of the molybdenum alloy may be any one of MoNb, MoW, MoTi and MoZr or a mixture of two of the above materials. The aforesaid layers may be formed in another manner, such as chemical vaporization method or physical deposition method and so on, which will not be described in detail here for simplicity.

(20) After forming of the above structure, the aforesaid structure in the present embodiment may be processed by a further patterning process, such as coating photoresist, exposure and development, and etching and so on, to obtain a finally desired pattern.

(21) The above conductive structure may be applied to a thin film transistor and a thin film transistor array substrate. Therefore, an embodiment of the invention also provides a thin film transistor which can generally comprise a gate electrode, a source electrode and a drain electrode; at least one of the gate electrode, the source and drain electrodes employ the above conductive structure. Other portion of the thin film transistor except for the portion employing the above conductive structure and the overall structure of the thin film transistor are not limited in the invention.

(22) An embodiment of the invention also provides a thin film transistor array substrate which can generally comprise a substrate; a thin film transistor array, gate lines and data lines formed on the substrate, the thin film transistor array comprising a plurality of thin film transistors, each of which comprises a gate electrode, a source electrode and a drain electrode; and a pixel electrode in one of regions defined by the gate lines and data lines intersecting the gate lines; at least one of the data lines, the source electrodes, the gate lines, the gate electrodes and the drain electrodes on the array substrate employs the above conductive structure. For example, the gate lines are connected with corresponding gate electrodes, the data lines are connected with corresponding source electrodes, and the pixel electrodes are connected with corresponding drain electrodes.

(23) In the embodiment, in the thin film transistor array substrate, a gate line and a gate electrode constitute a gate conductive structure, and a data line, a source electrode and a drain electrode constitute a data conductive structure. The gate lines are formed on the substrate and extend along a first direction, and the data lines are formed on the gate insulating layer and extend along a second direction. Here, the first direction may be perpendicular to the second direction. The drain electrode and the source electrode are disposed spaced apart from each other. A pixel electrode is formed in a pixel region defined by a gate line and a data line intersecting the gate line and electrically connected with a drain electrode.

(24) In the present embodiment, any one element in the gate conductive structure and the data conductive structure, such as the gate electrode, the gate line or drain electrode and so on, can employ the conductive structure as shown in FIG. 1.

(25) Hereinafter, a thin film transistor array substrate according to an embodiment of the invention will be described in detail with reference to FIG. 2.

(26) The array substrate as shown in FIG. 2 may be applied to a liquid crystal display or an organic light emitting display device, and comprises a base substrate 13 and at least one gate conductive structure 5 provided on the base substrate 13. Here, the gate conductive structure 5 comprises a gate electrode and a gate line; the gate electrode and/or the gate line may employ the conductive structure as shown in FIG. 1, that is, comprise a blocking layer, a diffusion prevention layer and a copper layer. Here, the blocking layer is formed on the base substrate 13 and its material may be molybdenum alloy (for example, one or more of MoNb, MoW, MoTi, MoZr and so on), and the atom percentage of Nb (or W, Ti, Zr and so on) in the alloy is in a range of 0.001 at % to 50 at %, for example. The thickness of the blocking layer is determined by desired interface state and etching status, for example, may be between 50 to 1000 . The diffusion prevention layer is formed on the blocking layer, and the diffusion prevention material is molybdenum (Mo), the thickness of the diffusion prevention layer is determined by desired interface state and etching status, for example, may be between 30 and 200 . The copper layer is formed of a material of copper metal or copper alloy and on the diffusion prevention layer.

(27) The gate conductive structure consisted of the blocking layer, the diffusion prevention layer and the copper layer can overcome the defect that the adhesiveness between the copper wire and the substrate base is bad in the existing technology; the blocking layer consisted of molybdenum alloy can improve the adhesiveness between the copper layer and the substrate and prevent copper ions from diffusing to the substrate; the diffusion prevention layer formed of molybdenum (Mo) material can prevent Nb (or W, Ti, Zr and so on) ions from diffusing to the copper layer, and thus prevent deterioration of the electricity performance and chemical corrosion resistance of the copper metal layer due to the aforesaid ion diffusion, and ensure the low resistance value characteristic of the copper metal layer. Meanwhile, the blocking layer, the diffusion prevention layer and the copper layer may have similar etched characteristics during an etching process so as to easily form a good pattern by an etching process, reducing a manufacturing cost.

(28) The array substrate shown in FIG. 2 further comprises a gate insulating layer 6 disposed on the base substrate 13, and the gate insulating layer 6 covers the gate conductive structure 5. A channel element (i.e., an active layer) is configured on the gate insulation layer 6 and comprises an intrinsic semiconductor layer 7 and an ohmic contact semiconductor layer 8. The ohmic contact semiconductor layer 8 is configured on the intrinsic semiconductor layer 7. Of course, the active layer may also comprise an organic semiconductor, a metal oxide semiconductor (such as IGZO) or the like.

(29) The array substrate shown in FIG. 2 further comprises at least one data conductive structure which is configured on the channel element. The data conductive structure comprises a data line 9a, a source electrode 9b and a drain electrode 9c. The data line 9a is disposed on the gate insulating layer 6. The source electrode 9b and the drain electrode 9c are disposed on the channel element, and the source electrode 9b is electrically connected with the data line 9a and is disposed spaced apart from the drain electrode 9c. Any one or more than two of the data line 9a, the source electrode 9b and the drain electrode 9c can employ the conductive structure shown in FIG. 1, that is, may comprises a blocking layer, a diffusion prevention layer and a copper layer. Here, the blocking layer is formed on the gate insulation layer 6 or the channel element, and its material may be molybdenum alloy (for example, one or more of MoNb, MoW, MoTi, MoZr and so on), and the atom percentage of Nb (or W, Ti, Zr and so on) in the alloy is in a range of 0.001 at % to 50 at %, for example. The thickness of the blocking layer is determined by desired interface state and etching status, for example, may be between 50 to 1000 . The diffusion prevention layer is formed on the blocking layer, and the material of the diffusion prevention is molybdenum (Mo), the thickness of the diffusion prevention layer is determined by desired interface state and etching status, for example, may be between 30 and 200 . The copper layer is formed on the diffusion prevention layer, and its material may be copper or copper alloy layer.

(30) The data conductive structure composed of the blocking layer, the diffusion prevention layer and the copper layer can overcome the defect that the adhesiveness at the interface between the copper conductor and the semiconductor layer is not good. The blocking layer composed of molybdenum alloy can overcome the defect that the adhesiveness at the interface between the copper conductor and the semiconductor layer is not good, and can prevent inter-diffusions of copper atoms and silicon atoms between the copper metal layer and the semiconductor layer, and reduce or avoid ions diffusion from adversely impacting the electricity performance of the semiconductor layer and the copper layer. The diffusion prevention layer formed of molybdenum (Mo) can prevent Nb (or W, Ti, Zr and so on) ions in the blocking layer from diffusing to the copper layer, prevent deterioration of the electricity performance and chemical corrosion resistance of the copper metal layer, and ensure a lower resistance value of the copper metal layer. Meanwhile, the blocking layer, the diffusion prevention layer and the copper layer may have similar etched characteristics during an etching process, so as to easily form a good pattern by the etching process and reduce manufacturing costs.

(31) The array substrate shown in FIG. 2 further comprises a protection layer 10, which is disposed on the data line 9a, the source and drain electrodes 9b and 9c and the gate insulating layer 6; a pixel electrode 11 is disposed on the protection layer 10 and is electrically connected with the drain electrode 9c through a via hole 12.

(32) Other portion of the array substrate described in the embodiment of the invention except the portion employing the above conductive structure and the overall structure of the thin film transistor array substrate are not limited to the above configurations, and for example, may further comprise a common electrode to form an array substrate in an ADS type, or may form an array substrate in a color filter on array (COA) form and so on, which is not described in detail here.

(33) An embodiment of the invention further provides a display device, and the display device comprises a display device employing any one of the thin film transistor array substrates described in the above embodiment. The display device may be a liquid crystal device, an electronic paper display device, or OLED display device and so on, and for example, may be used to any products or components having a display function, such as a mobile telephone, a tablet computer, a television set, a notebook computer, a digital picture frame, a navigator and so on.

(34) The above description involves only illustrative examples of the present invention. It should be noted that those skilled in the related art, without departing from the spirit of the invention, can make modification or variation, which should be deemed as falling within the protection scope of the invention.