A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.

According to example embodiments, an electronic device includes channel layer including a graphene layer electrically contacting a quantum dot layer including a plurality of quantum dots, a first electrode and a second electrode electrically connected to the channel layer, respectively, and a gate electrode configured to control an electric current between the first electrode and the second electrode via the channel layer. A gate insulating layer may be between the gate electrode and the channel layer.

A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode. The pn light-emitting body includes a p-type nitride semiconductor layer and an n-type nitride semiconductor layer to emit a light beam having an energy value higher than an electron trapping level existing in the semiconductor stacked body, in which the p-type nitride semiconductor layer of the pn light-emitting body is electrically connected to the gate electrode, and functions as a gate of the transistor.

A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) n-type modulation doped quantum well structure (MDQWS) structure with n-type charge sheet, ii) p-type MDQWS, iii) undoped spacer layer formed on the n-type charge sheet, iv) p-type layer(s) formed on the undoped spacer layer, v) p-type etch stop layer formed on the p-type layer(s) of iv), and vi) p-type layers (including p-type ohmic contact layer(s)) formed on the p-type etch stop layer. An etch operation removes the p-type layers of vi) for a gate region of an n-channel HFET with an etchant that automatically stops at the p-type etch stop layer. Another etch operation removes the p-type etch stop layer to form a mesa at the p-type layer(s) of iv) which defines an interface to the gate region of the n-channel HFET, and a gate electrode is formed on such mesa.

LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer is bonded to an LED wafer and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. A single dielectric layer in a panel may encapsulate all the RGB modules to form a compact and inexpensive panel. Various addressing techniques are described for both a color display and a lighting panel. Various circuits are described for reducing the sensitivity of the LED to variations in input voltage.

A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

A backplane for a flat panel display apparatus, includes: a thin film transistor (TFT) on a substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; a light-blocking layer between the substrate and the TFT; a first insulating layer between the light-blocking layer and the TFT; a capacitor including a first electrode on the same plane as the light-blocking layer, and a second electrode on the first electrode, wherein the first insulating layer is between the first electrode and the second electrode; and a pixel electrode on the same plane as the light-blocking layer.

An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

An optoelectronic device comprising a mesa structure including: a first and a second semiconductor portions forming a p-n junction, a first electrode electrically connected to the first portion which is arranged between the second portion and the first electrode, the device further comprising: a second electrode electrically connected to the second portion, an element able to ionize dopants of the first and/or second semiconductor portion through generating an electric field in the first and/or second semiconductor portion and overlaying at least one part of the side flanks of at least one part of the first and/or second semiconductor portion and of at least one part of a space charge zone formed by the first and second semiconductor portions, upper faces of the first electrode and of the second electrode form a substantially planar continuous surface.