Addressable actuator and arrays thereof are described. Actuators may be dielectric elastomer actuators (DBAs). An addressable actuator may include a compliant substrate, with an optical receiver integrated with a first region of the compliant substrate and an actuator integrated with a second region of the compliant substrate, with the optical receiver coupled to the actuator. The optical receivers may comprise percolating networks of semiconductor materials, such as photoconductive channels of zinc oxide nanowires, which may be embedded in a compliant substate, or one or more compliant layers (which may be formed on a substrate). Compliant substrates or layers may include complaint materials such as an elastomer. An actuator array may comprise multiple of the actuators, with each actuator being independently optically addressable. A system may include light emitting devices optically coupled to respective optical receivers to control actuation of the actuators using light.

A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.

A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

A device includes a gate electrode, a gate dielectric layer, a 2-D material layer, and source/drain contacts. The gate dielectric layer is over the gate electrode. The 2-D material layer is over the gate dielectric layer, in which the 2-D material layer includes a channel region and source/drain regions on opposite sides of the channel region. The source/drain contacts are disposed on the source/drain regions of the 2-D material layer, respectively, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer.

A device includes a gate electrode, a gate dielectric layer, a 2-D material layer, and source/drain contacts. The gate dielectric layer is over the gate electrode. The 2-D material layer is over the gate dielectric layer, in which the 2-D material layer includes a channel region and source/drain regions on opposite sides of the channel region. The source/drain contacts are disposed on the source/drain regions of the 2-D material layer, respectively, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer.

A transistor includes a dielectric layer, a channel region, a gate electrode and source and drain electrodes. The channel region is disposed over the first surface of the dielectric layer. The gate electrode wraps around the channel region, wherein a portion of the gate electrode is disposed under the first surface of the dielectric layer. The source and drain electrodes are disposed at opposite sides of the gate electrode and over the first surface of the dielectric layer.

A thin film transistor includes an active layer of an oxide semiconductor, a gate electrode provided on or under the active layer while being spaced apart from the active layer and overlapping with at least a portion of the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes copper (Cu).