A solar cell is provided with an electrode layer on a photovoltaic conversion section including a crystalline silicon substrate. Deposition of the electrode layer is performed by a deposit-up method with a substrate being mounted in such a manner that an opening edge portion of a mask plate having an opening is in contact with the substrate. The opening edge portion of the mask plate has a tapered surface at a part that is in contact with first principal surface of the substrate, the tapered surface conforming to a deflection angle at a peripheral end of the substrate. A solar cell having a large effective area can be prepared by suppressing deposition of electrode layer on mask-covered region due to penetration.

A manufacturing method includes steps of forming a texture on a surface of a single-crystalline silicon substrate, cleaning the surface of the single-crystalline silicon substrate using ozone, depositing an intrinsic silicon-based layer on the texture on the single-crystalline silicon substrate, and depositing a conductive silicon-based layer on the intrinsic silicon-based layer, in this order. The single-crystalline silicon substrate before deposition of the intrinsic silicon-based layer has a texture size of less than 5 m. A recess portion of the texture has a curvature radius of less than 5 nm. After deposition of at least a part of the intrinsic silicon-based layer and before deposition of the conductive silicon-based layer, the intrinsic silicon-based layer is subjected to a plasma treatment in an atmosphere of a gas mainly composed of hydrogen.

The present invention relates to a plasma texturing method for silicon based solar cells and the nanostructured silicon solar cells produced thereof. The silicon based solar cell comprises a silicon substrate having in at least part of its surface conical shaped nanostructures having an average height between 200 and 450 nm and a pitch between 100 and 200 nm, thereby achieving low reflectance and minimizing surface charge recombination.

An avalanche photodiode includes a GeOI substrate; an IGe absorption layer configured to absorb an optical signal and generate a photo-generated carrier; a first p-type SiGe layer, a second p-type SiGe layer, a first SiGe layer, and a second SiGe layer, where a Si content in any one of the SiGe layers is less than or equal to 20%; a first SiO.sub.2 oxidation layer and a second SiO.sub.2 oxidation layer; a first taper type silicon Si waveguide layer and a second taper type silicon Si waveguide layer; a heavily-doped n-type silicon Si multiplication layer; and anode electrodes and a cathode electrode.

A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.

After forming an absorber layer containing cracks over a back contact layer, a passivation layer is formed over a top surface of the absorber layer and interior surfaces of the cracks. The passivation layer is deposited in a manner such that that the cracks in the absorber layer are fully passivated by the passivation layer. An emitter layer is then formed over the passivation layer to pinch off upper portions of the cracks, leaving voids in lower portions of the cracks.

A solar cell element comprises a silicon substrate, a passivation layer, a first conductive portion, an electrode, and a second conductive portion. The silicon substrate has a plurality of recessed portions in one main surface. The passivation layer is located on the one main surface and has holes in positions corresponding to the recessed portions. The first conductive portion is located in each of the holes. The electrode is connected to the first conductive portion while being located on the passivation layer, and contains aluminum. The second conductive portion is connected to each of the silicon substrate and the first conductive portion while being located in a region in each of the recessed portions, and contains aluminum and silicon. A void in which the second conductive portion is not located is present in the region in each of the recessed portions.

A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Fabrication methods for forming self aligned contacts for back contact solar cells are provided.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as holes, effectively increase the absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. Their thickness dimensions allow them to be conveniently integrated on the same Si chip with CMOS, BiCMOS, and other electronics, with resulting packaging benefits and reduced capacitance and thus higher speeds.