A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

A power transistor device such as, e.g., a power MOS device includes a control line for controlling a device current flowing through the device. The device includes a plurality of cells contributing respective fractions of the device current with a plurality of control terminals each adapted to control current flow through one of the cells. The device includes respective decoupling resistors between the control line and the control terminals. Upon failure of one of the cells, the other non-failed cells can be rendered nonconductive by a switch-off control signal applied via the control line.

A method of manufacturing a semiconductor substrate includes (a) preparing a substrate having a front surface, a back surface located on an opposite side of the front surface, a first sloped portion connected to the front surface, and a second sloped portion connected to the back surface, (b) forming an epitaxial layer on the front surface and the first sloped portion, (c) after the (b), polishing the back surface, and (d) after the (c), grinding the first sloped portion.

A radiation hardened semiconductor device including a heavily doped substrate of a semiconductor device, a drift layer having a substantially uniform doping concentration and a thickness is provided. The doping concentration and the thickness of the drift layer are such that when the semiconductor device is operating at a maximum voltage rating, an electrical field profile in the drift layer extends less than 80% of the thickness of the drift layer, providing the radiation hardened nature of the device.

The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

A power converter module includes a baseplate, a substrate on the baseplate, one or more silicon carbide switching components on the substrate, and a housing over the baseplate, the substrate, and the one or more silicon carbide switching components. The housing has a footprint less than 25 cm.sup.2. Including a baseplate in a power converter module with a footprint less than 25 cm.sup.2 runs counter to accepted design principles for silicon and silicon carbide-based power converter modules, but may improve performance of the power converter module and/or decrease the cost of the power converter module.

A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

The present invention provides a method of forming a passivation layer of a MOS device, and a MOS device. The method of forming a passivation layer of a MOS device includes: forming a substrate; forming a dielectric on the substrate; patterning the dielectric to expose a part of the substrate; forming a metal on the exposed part of the substrate, and the dielectric; forming a TEOS on the metal; forming a PSG on the TEOS; and forming a silicon nitrogen compound on the PSG. Therefore, the cracks problem of the passivation can be alleviated.