A semiconductor device having a first load terminal, a second load terminal and a semiconductor body is presented. The semiconductor body comprises an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the active region. The semiconductor body includes a drift layer arranged within both the active region and the junction termination region and having dopants of a first conductivity type at a drift layer dopant concentration of equal to or less than 10.sup.14 cm.sup.3; a body zone arranged in the active region and having dopants of a second conductivity type complementary to the first conductivity type and isolating the drift layer from the first load terminal; a guard zone arranged in the junction termination region and having dopants of the second conductivity type and being configured to extend a depletion region formed by a transition between the drift layer and the body zone; a field stop zone arranged adjacent to the guard zone, the field stop zone having dopants of the first conductivity type at a field stop zone dopant concentration that is higher than the drift layer dopant concentration by a factor of at least 2; a low doped zone arranged adjacent to the field stop zone, the low doped zone having dopants of the first conductivity type at a dopant concentration that is lower than the drift layer dopant concentration by a factor of at least 1.5, wherein the body zone, the guard zone, the field stop zone and the low doped zone are arranged in the semiconductor body such that they exhibit a common depth range (DR) of at least 1 m along a vertical extension direction (Z).

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.

A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. A switch comprises a first FET in series with a second FET, and a buffer with an output terminal and an input terminal. The drain terminal of the first FET is connected to the source terminal of the second FET. The input terminal is coupled to the drain terminal of the second FET. At least one of: the first FET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the first FET; and, the second SFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the second FET.

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.

An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.