Photovoltaic cells having copper contacts can be made by using copper nanoparticles during their fabrication. Such photovoltaic cells can include a copper-based current collector located on a semiconductor substrate having an n-doped region and a p-doped region. The semiconductor substrate is configured for receipt of electromagnetic radiation and generation of an electrical current therefrom. The copper-based current collector includes an electrically conductive diffusion barrier disposed on the semiconductor substrate and a copper contact disposed on the electrically conductive diffusion barrier. The copper contact is formed from copper nanoparticles that have been at least partially fused together. The electrically conductive diffusion barrier limits the passage of copper therethrough.

Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of Si.sub.xGe.sub.1-x passivated by amorphous Si.sub.yGe.sub.1-y:H.

One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100 C. to 200 C., and the step of depositing the layer of silicon oxynitride includes using N.sub.2O and SiH.sub.4 as precursor gasses in an N.sub.2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N.sub.2O to SiH.sub.4 below 2.

A solar cell includes a solar cell substrate including a principal surface on which a p-type surface and an n-type surface are exposed, a p-side electrode formed on the p-type surface and including a first linear portion linearly extending in a first direction, and an n-side electrode formed on the n-type surface and including a second linear portion linearly extending in the first direction and arranged next to the first linear portion in a second direction orthogonal to the first direction. Corners of a tip end of at least one of the first and second linear portions are formed in a chamfered shape.

A conductive paste composition contains a source of an electrically conductive metal, a first oxide component comprising an alkali metal vanadium oxide composition, an optional second non-oxide, non-metal component, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the paste composition on a semiconductor device substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and establish electrical contact between it and the substrate.

Methods for forming passivated contacts include implanting compound-forming ions into a substrate to about a first depth below a surface of the substrate, and implanting dopant ions into the substrate to about a second depth below the surface. The second depth may be shallower than the first depth. The methods also include annealing the substrate.

Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.

A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure.

A method of fabricating a passivated contact for a photovoltaic cell includes depositing a tunneling oxide layer on a first face of a substrate. An amorphous silicon layer is then deposited on top of the tunneling oxide layer. An aluminum layer is screen printed on top of the amorphous silicon layer. The aluminum layer is configured to serve as a crystallization catalyst for the amorphous silicon layer. The amorphous silicon layer and the aluminum layer are then heated to a crystallization temperature that is configured to cause the amorphous silicon to crystallize and to sinter the aluminum layer.