In an embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor body including a first doped region of a first conductivity type and a second doped region of a second conductivity type. The semiconductor device may include a metal structure, in the semiconductor body, overlying the second doped region. The metal structure may include a first sidewall adjacent a first portion of the first doped region, a second sidewall adjacent a second portion of the first doped region, and a third sidewall adjacent the second doped region. The semiconductor device may include a Schottky contact including a junction of the third sidewall of the metal structure with the second doped region.

Monolithic devices including combinations of diodes, with electrical components fabricated and electrically connected among them, are described herein, along with process techniques for forming the devices. An example method of forming a monolithic semiconductor circuit includes forming a plurality of layers of semiconductor materials over a substrate, forming Schottky diode contacts for a Schottky diode on a first subset of the plurality of layers, and forming PIN diode contacts for a PIN diode on a second subset of the plurality of layers. The layers can include an etch stop layer, and the etch stop layer can be positioned between the first subset of the plurality of layers and the second subset of the plurality of layers. The method can also include etching the layers of semiconductor materials down to the etch stop layer after forming the Schottky diode contacts and before forming the PIN diode contacts.

A semiconductor device includes a field insulating film formed on an epitaxial layer, a front surface electrode riding onto an inner peripheral end of the field insulating film, and an outer peripheral electrode riding onto an outer peripheral end of the field insulating film. To a surface portion of the epitaxial layer, connected is the front surface electrode, and in the surface portion of the epitaxial layer, formed is a well region extending up to the outside of the outer peripheral end of the front surface electrode. A moisture-resistant insulating film is formed so as to cover the outer peripheral end of the front surface electrode, an inner peripheral end of the outer peripheral electrode, and the field insulating film. On the moisture-resistant insulating film, formed is a semi-insulating film connected to the front surface electrode and the outer peripheral electrode which are exposed from the moisture-resistant insulating film.

A semiconductor device includes a field insulating film formed on an epitaxial layer, a front surface electrode riding onto an inner peripheral end of the field insulating film, and an outer peripheral electrode riding onto an outer peripheral end of the field insulating film. To a surface portion of the epitaxial layer, connected is the front surface electrode, and in the surface portion of the epitaxial layer, formed is a well region extending up to the outside of the outer peripheral end of the front surface electrode. A moisture-resistant insulating film is formed so as to cover the outer peripheral end of the front surface electrode, an inner peripheral end of the outer peripheral electrode, and the field insulating film. On the moisture-resistant insulating film, formed is a semi-insulating film connected to the front surface electrode and the outer peripheral electrode which are exposed from the moisture-resistant insulating film.

The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

A thin-film integrated circuit comprising a first semiconductor device, a second semiconductor device, a first resistor, and a second resistor is provided. A semiconducting region of the first semiconductor device, a resistor body of the first resistor, a semiconducting region of the second semiconductor device, and a resistor body of the second resistor are formed from at least one of a first source material and a second source material, and a material of the resistor body of the first resistor and a material of the resistor body of the second resistor have different electrical properties.

A thin-film integrated circuit comprising a first semiconductor device, a second semiconductor device, a first resistor, and a second resistor is provided. A semiconducting region of the first semiconductor device, a resistor body of the first resistor, a semiconducting region of the second semiconductor device, and a resistor body of the second resistor are formed from at least one of a first source material and a second source material, and a material of the resistor body of the first resistor and a material of the resistor body of the second resistor have different electrical properties.

A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.

The present disclosure provides a light-emitting substrate, a backlight and a display device. The light-emitting substrate includes a light-emitting region and a peripheral region surrounding the light-emitting region. The peripheral region includes a first area, the first area is located between a first side of the light-emitting substrate and the light-emitting region, the light-emitting substrate further includes a first signal line, the first signal line includes at least one selected from a group consisting of a first portion and a second portion, the first portion of the first signal line extends along a first direction in the first area, the second portion of the first signal line extends into the light-emitting region, the first portion and the second portion of the first signal line are connected when the first signal line includes the first portion and the second portion.

Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.