There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.

An imaging device having a pixel including: a photoelectric converter that generates an electric signal through photoelectric conversion of incident light; a first transistor that has a gate coupled to the photoelectric converter and that amplifies the electric signal; and a second transistor that has a gate coupled to the photoelectric converter, one of a source and a drain of the second transistor being coupled to the photoelectric converter. The imaging device further includes a voltage supply circuit configured to supply two or more different voltages to the other of the source and the drain of the second transistor.

The present disclosure relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus, in which both oblique light characteristics and sensitivity can be improved. The solid-state imaging device includes pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix and multi-stage light shielding walls are provided between the pixels. The present disclosure is applicable to, for example, a back-illuminated type solid-state imaging device and the like.

An optical sensor, especially an artificial retina, that includes at least one photosensitive cell. Each cell includes a integration capacitor, a read circuit the operation of which depends on the charge of the integration capacitor, at least one MOS transistor operating subthreshold, and the drain-source current of which influences the charge on the integration capacitor, and at least one photodiode operating in photovoltaic mode and connected to the gate of this transistor, such that the drain-source current of the MOS transistor depends on the optical power received by the photodiode.

In an imaging apparatus, each of a plurality of pixels has a first semiconductor area having a first conductivity type, a floating diffusion area, and a transfer gate positioned between the first semiconductor area and the floating diffusion area. In a part of the plurality of pixels, a partial area of the first semiconductor area receives a potential supplied from a contact. The part of the plurality of pixels further has a second semiconductor area having a second conductivity type positioned between the partial area and the transfer gate in a planar view.

There is provided a solid-state image pickup element including: a photodiode configured to convert incident light into a photocurrent; an amplification transistor configured to amplify a voltage between a gate having a potential depending on the photocurrent and a source having a predetermined reference potential and output the amplified voltage from a drain; and a potential supply section configured to supply an anode of the photodiode and a back-gate of the amplification transistor with a predetermined potential lower than the reference potential.

An imaging device includes an image detector that includes an array of digital pixels, each digital pixel including an output that provides a digital pixel output pulse each time a charge stored in the digital pixel exceeds a threshold and a readout integrated circuit (ROIC) connected to the output of each of the digital pixels to receive the digital pixel output pulse from each pixel, the ROIC including a plurality of accumulators, each of the plurality of accumulators associated with a respective digital pixel. The imaging device also includes a controller that reads the accumulators to determine a number of digital pixel output pulses stored by the accumulators without stopping the generation of digital pixel output pulses.

An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.

In a general aspect, integrated spatial phase wafer-level imaging is described. In some aspects, an integrated imaging system an integrated image sensor and an edge processor. The integrated image sensor may include: a polarizer pixel configured to filter electromagnetic (EM) radiation and to allow filtered EM radiation having a selected polarization state to pass therethrough; a radiation-sensing pixel configured to detect the filtered EM radiation and to generate a signal in response to detecting the filtered EM radiation; and readout circuitry configured to perform analog preprocessing on the signal generated by the radiation-sensing pixel. The edge processor may be configured to: generate first-order primitives and second-order primitives based on the analog preprocessed signal from the readout circuitry; and determine a plurality of features of an object located in a field-of-view of the radiation-sensing pixel based on the first-order primitives and the second-order primitives.

In an example embodiment, an image processing device includes a pixel array including pixels two-dimensionally arranged and configured to capture an image, each of the pixels including a plurality of photoelectric conversion elements and an image data processing circuit configured to generate image data from pixel signals output from the pixels. The image processing device further includes a color data processing circuit configured to extract color data from the image data and output extracted color data. The image processing device further includes a depth data extraction circuit configured to extract depth data from the image data and output extracted depth data. The image processing device further includes an output control circuit configured to control the output of the color data and the depth data.