A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

A method for manufacturing a semiconductor device may include: forming a plurality of stacked structures over a substrate, the substrate including one or more peripheral circuit regions and one or more cell regions, the stacked structures including first conductive lines and initial memory cells respectively disposed over the first conductive lines, each of the stacked structures extending in a first direction; forming a first insulating layer between the stacked structures; forming second conductive lines over the stacked structures and the first insulating layer, each of the second conductive lines extending in a second direction; forming memory cells by etching the initial memory cells exposed by the second conductive lines; forming a second insulating layer between the second conductive lines and between the memory cells; and removing the first conductive lines, the memory cells, and the second conductive lines in the peripheral circuit regions.

A ferromagnetic free layer, a preparation method and an application thereof are provided, where the ferromagnetic layer includes a magnetic film alloy, and the magnetic film alloy includes multiple layers of laminated films. A thickness of each of the films decreases gradually from a first end to a second end of the magnetic film alloy, so as to break in-plane structural symmetry of the magnetic film alloy, and the films include heavy metal films and ferromagnetic metal films, where out-of-plane crystal symmetry of the magnetic film alloy is broken by means of component gradients. When a current is applied in plane of the magnetic film alloy, a spin orbit torque will be generated, which directly drives the magnetic moment of the magnetic film alloy to undergo a deterministic magnetization reversal.

An approach providing a semiconductor structure that provides a self-leveling, flowable, dielectric material for a gap fill material between vertical structures in many emerging non-volatile memory devices that are being formed with vertical structures for increasing memory device density. The semiconductor structure provides a flat dielectric surface between a plurality of contacts in a back end of the line metal layer in both the memory region and in the logic region of the semiconductor structure. The semiconductor structure includes a first portion of the plurality of contacts that each connect to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the contacts that each connect to a pillar-based memory device in the array of memory devices reside in a conventional interlayer dielectric material under the self-leveling dielectric material. The flowable, self-leveling material provides a flat dielectric surface during contact formation.

A method for fabricating a semiconductor device including a plurality of memory cells. The method includes: forming a first electrode layer; forming an initial Si-containing layer over the first electrode layer; performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO.sub.2) and form a Si-containing layer under the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.

Computing devices, such as mobile computing devices, have access to one or more image sensors that can capture images with multiple subjects. Some of these subjects may be known to the user capturing an image with the image sensor. The user may prefer to have the captured image data be optimized around the known subjects. Low-power, fast-response machine learning logic can be configured to allow for the generation of a plurality of inference data. This inference data can be utilized along with other sensor data, such as a motion sensor, for the generation of one or more image sensor configuration changes that may be implemented to optimize the subsequent capture of image data. This cycle of image data analysis, image sensor optimization, and subsequent capture can continue multiple times until a threshold of optimization or time is met. The captured image data optimized around the known subjects is then stored.

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

A spin-current magnetization rotational element includes a spin orbit torque wiring extending in a first direction and a first ferromagnetic layer disposed in a second direction intersecting the first direction of the spin orbit torque wiring, the spin orbit torque wiring having a first surface positioned on the side where the first ferromagnetic layer is disposed, and a second surface opposite to the first surface, and the spin orbit torque wiring has a second region on the first surface outside a first region in which the first ferromagnetic layer is disposed, the second region being recessed from the first region to the second surface side.

Systems for performing source line sensing of magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a MeRAM circuit includes a plurality of voltage controlled magnetic tunnel junction bits, application of a voltage with opposite polarity increases the perpendicular magnetic anisotropy and magnetic coercivity of the free layer through the VCMA effect, each magnetoelectric junction is connected to the drain of an MOS transistor, the combination includes a MeRAM cell, each MeRAM cell includes three terminals, each connected respectively to a bit line, a source line, and at least one word line, in an array, a pulse generator and a write MOS transistor connected to the bit line and the source line, a sense amplifier and a sense MOS transistor connected to the source line and the bit line, and a current source circuit connected to the source line and the reference line.