A method for manufacturing a Hall sensor, an insulation layer being initially applied to a wafer including an ASIC or integrated into the wafer, a Hall layer, for example, made of InSb or another III-V semiconductor material, being situated thereon, and this Hall layer being at least sectionally recrystallized with the aid of a laser. The insulation layer may be porous or may include a cavity or reflective layer for thermal protection of the ASIC.

A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.

Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element including material layers over a substrate; forming a hard mask layer including a metal over the material layers; selectively etching the hard mask layer to form an etched hard mask layer; etching the material layers by using the etched hard mask layer as an etch barrier, the etching of the material layers providing an etch byproduct formed on sidewalls of the etched material layers and the etch byproduct including a material that is more readily oxidized than the metal of the hard mask layer; and performing a treatment using a gas or plasma to suppresses oxidation of the hard mask layer and facilitate oxidation of the etch byproducts.

A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. The seed layer includes first and second seed layer separated by a surface smoother, such as a surfactant layer. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer may include: a first under layer including a silicon-based alloy; a second under layer including a metal; and a blocking layer interposed between the first under layer and the second under layer and including an amorphous material.

A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

The present invention is directed to an MTJ memory element, which comprises a magnetic fixed layer structure formed on top of a seed layer structure that includes a first seed layer and a second seed layer. The first seed layer includes one or more layers of nickel interleaved with one or more layers of a transition metal, which may be tantalum, titanium, or vanadium. The second seed layer is made of an alloy or compound comprising nickel and another transition metal, which may be chromium, tantalum, or titanium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first type material interleaved with layers of a second type material with at least one of the first and second type materials being magnetic. The first and second type materials may be cobalt and nickel, respectively.