A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.

A semiconductor device includes first and second contact plugs in an insulating layer that is on a substrate, the first and second contact plugs spaced apart from each other. A spin-orbit torque (SOT) line on the insulating layer and overlapping the first and second contact plug is provided. A magnetic tunnel junction (MTJ) is on the SOT line. An upper electrode is on the MTJ. Each of the first and second contact plugs includes a recess region adjacent the SOT line. A sidewall of the recess region is substantially coplanar with a side surface of the SOT line and a side surface of the MTJ.

A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.

The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a topological insulator (TI) modulation layer. The TI modulation layer comprises a plurality of bismuth or bismuth-rich composition modulation layers, a plurality of TI lamellae layers comprising BiSb having a (012) crystal orientation, and a plurality of texturing layers. The TI lamellae layers comprise dopants or clusters of atoms, the clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material. The clusters of atoms are configured to have a grain boundary glass forming temperature of less than about 400° C. Doping the TI lamellae layers comprising BiSb having a (012) crystal orientation with clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material enable the SOT MTJ device to operate at higher temperatures while inhibiting migration of Sb from the BiSb of the TI lamellae layers.

According to one embodiment, in a nonvolatile semiconductor memory device, in a cell block, a local bit line is connected to a bit line via a select transistor. The local bit line extends in a third direction. A local source line is connected to a source line and extends in the third direction. A plurality of memory cells are connected in parallel between the local source line and the local bit line. Each of the memory cells includes a cell transistor and a resistance change element. The cell transistor has a gate connected to a corresponding one of the word lines and one end connected to one of the local bit line or the local source line. The resistance change element is connected between the other end of the cell transistor and the other one of the local bit line or the local source line.

A magnetic domain wall movement element includes a magnetoresistance effect part, a first electrode, a second electrode, a third electrode, a first magnetization fixed layer, and a second magnetization fixed layer. The magnetoresistance effect part includes a reference layer, a magnetic domain wall movement layer, and a non-magnetic layer. The magnetic domain wall movement layer has a first region and second region in which a magnetization direction is fixed, and a third region in which a magnetization direction is variable. The reference layer overlaps at least part of the first region and the second region in a plan view in a first direction, and at least part of the first region and the second region is shorter than the third region in a third direction orthogonal to the first direction and the second direction.

A storage element is provided. The storage element includes a memory layer; a fixed magnetization layer; an intermediate layer including a non-magnetic material; wherein the intermediate layer is provided between the memory layer and the fixed magnetization layer; wherein the fixed magnetization layer includes at least a first magnetic layer, a second magnetic layer, and a non-magnetic layer, and wherein the first magnetic layer includes a CoFeB composition. A memory apparatus and a magnetic head are also provided.

A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.

Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.