A tunneling magnetoresistance (TMR) sensor device is disclosed that includes four or more TMR resistors. The TMR sensor device comprises a first TMR resistor comprising a first TMR film, a second TMR resistor comprising a second TMR film different than the first TMR film, a third TMR resistor comprising the second TMR film, and a fourth TMR resistor comprising the first TMR film. The first, second, third, and fourth TMR resistors are disposed in the same plane. The first TMR film comprises a synthetic anti-ferromagnetic pinned layer having a magnetization direction of the reference layer orthogonal to a free layer. The second TMR film comprises a double synthetic anti-ferromagnetic pinned layer having a magnetization direction of the reference layer orthogonal to the magnetization of a free layer, but opposite to the magnetization direction of the reference layer of the first TMR film.

A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

An etching method includes: preparing a workpiece including a metal multilayer film having a magnetic tunnel junction and a mask formed by an inorganic material on the metal multilayer film; and etching the metal multilayer film by plasma of a mixed gas of ethylene gas and oxygen gas using the mask.

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

In an exchange coupling film that has a large magnetic field (Hex) in which the direction of magnetization of a fixed magnetic layer is reversed, high stability under high temperature conditions, and excellent strong-magnetic field resistance, an antiferromagnetic layer, a fixed magnetic layer, and a free magnetic layer are stacked, the antiferromagnetic layer is composed of a PtCr layer and an XMn layer (where X is Pt or Ir), the XMn layer is in contact with the fixed magnetic layer, and the fixed magnetic layer is made of iron, cobalt, an iron-cobalt alloy, or an iron-nickel alloy.

A true random number generator (TRNG) device having a magnetic tunnel junction (MTJ) structure coupled to a domain wall wire. The MTJ structure is formed of a free layer (FL) and a reference layer (RL) that sandwiches a tunnel barrier layer. The free layer has anisotropy energy sufficiently low to provide stochastic fluctuation in the orientation of the magnetic state of the free layer via thermal energy. The domain wall wire is coupled to the MTJ structure. The domain wall wire has a domain wall. Movement of the domain wall tunes a probability distribution of the fluctuation in the orientation of the magnetic state of the free layer. The domain wall can be moved by application of a suitable current through the wire to tune the probability distribution of 1's and 0's generated by a readout circuit of the TRNG device.

A random number generation unit and a computing system using the same, the unit including a magnetic tunnel junction element and being capable of developing the characteristics required for the execution of probabilistic computing and operating at a higher speed. A magnetic tunnel junction element includes a fixed layer having a ferromagnet and having a magnetization direction fixed substantially, a free layer having a ferromagnet and having a magnetization direction varying with a first time constant, and a barrier layer disposed between the layers configured with an insulator. The magnetic tunnel junction element has a shift magnetic field of an absolute value of 20 millitesla or smaller. The fixed layer has a plurality of ferromagnetic and non-magnetic coupling layers laminated one upon another, and ferromagnetic layers adjacent to each other among the respective ferromagnetic layers are coupled in terms of magnetization by the non-magnetic coupling layers in an antiparallel manner.

A magnetoresistive effect element includes a magnetization fixed layer, a magnetization free layer, and a non-magnetic spacer layer that is stacked between the magnetization fixed layer and the magnetization free layer. The magnetization free layer includes a first free layer and a second free layer that are formed of a ferromagnetic material, and a magnetic coupling layer that is stacked between the first free layer and the second free layer. The first free layer and the second free layer are magnetically coupled to each other by exchange coupling via the magnetic coupling layer such that magnetization directions of the first free layer and the second free layer are antiparallel to each other. The magnetic coupling layer is a non-magnetic layer that includes Ir and at least one of the following elements: Fe, Co and Ni.

A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.

In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer directly overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer. A maximum width of the BEVA is less than a width of the data storage structure.